Abstract: System for reducing power consumption in MPEG-2 compliant video encoder circuitry employs logic for controlling first clock signals input to functional I, HSU and RSU blocks and functional sub-units performing specific tasks therein. Second clock signals are continuously input to a processing detection circuits requiring continuous clock inputs throughout video encode operations for a functional sub-unit. A trigger signal is asserted by the sub-unit itself or, an external processor, to indicate idle or active processing for that particular sub-unit. The combination of the second clock signals and receipt of the trigger signal enable the sub-unit to generate a sleep signal for that sub-unit which is input to a clock control circuit to either enable input of first clock signals to the functional sub-unit during active processing or, disable input of the first clock signal during idle, in-active processing periods, for as long as the trigger signal is asserted.

Abstract: Method and apparatus for detecting and correcting error in an uncompressed digital video image data stream. The method and apparatus identify error or partial picture scenarios. Each of the possible error or partial picture scenarios is identified in a Partial Picture Repair Unit, which causes error processing of the uncompressed video input stream, resulting in the creation of a repaired data stream on the repaired pixel bus. The repair begins upon detection of an erroneous picture, field, or line. Processing for that picture, field or line is stopped upon detection of an error in the synchronization signals, and processing is resumed when the end of line, end of field, or end of picture indicator is detected.

Abstract: Method and apparatus for detecting and correcting error in an uncompressed digital video image data stream. The method and apparatus identify error or partial picture scenarios. Each of the possible error or partial picture scenarios is identified in a Partial Picture Repair Unit, which causes error processing of the uncompressed video input stream, resulting in the creation of a repaired data stream on the repaired pixel bus. The repair begins upon detection of an erroneous picture, field, or line. Processing for that picture, field or line is stopped upon detection of an error in the synchronization signals, and processing is resumed when the end of line, end of field, or end of picture indicator is detected.

Abstract: Disclosed is a digital video encoder processor for discrete cosine transform encoding. The discrete cosine transform encoding includes the encoding steps of (1) determining the discrete cosine transform field or frame type, (2) addressing individual pixels as either (i) vertically adjacent pixels on consecutive Odd and Even field lines, or (ii) vertically adjacent pixels on consecutive Odd field lines, then consecutive Even field lines; or (iii) vertically adjacent pixels on consecutive Even field lines, then consecutive Odd field lines. These subtractions may be performed between (i) consecutive lines, (ii) odd lines, or (iii) even lines. The next step is finding the smallest variance of the above subtractions to determine the discrete cosine transform coding type. The subtractions are carried out in a dynamically partitionable processor having a plurality of datapaths.