Abstract: A two-way communication device has a master transmitter connected to at least one slave transmitter by an active connection wire. The master transmitter and the slave transmitter have a common reference. The master transmitter can transmit a master signal to the slave transmitter and the slave transmitter can transmit a slave signal to the master transmitter. The master signal is a digital modulation in voltage. The slave signal is a digital modulation in current.

Abstract: A two-way communication device has a master transmitter connected to at least one slave transmitter by an active connection wire. The master transmitter and the slave transmitter have a common reference. The master transmitter can transmit a master signal to the slave transmitter and the slave transmitter can transmit a slave signal to the master transmitter. The master signal is a digital modulation in voltage. The slave signal is a digital modulation in current.

Abstract: A two-way communication device has a master transmitter (SysM1, TRM1, SysM2, TRM2) connected to at least one slave transmitter (SysS1, TRS1, SysS2, TRS2) by an active connection wire. The master transmitter and the slave transmitter have a common reference (GND). The master transmitter can transmit a master signal (S1) to the slave transmitter and the slave transmitter can transmit a slave signal (S2) to the master transmitter. The master signal (S1) is a digital modulation in voltage. The slave signal (S2) is a digital modulation in current.

Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

Abstract: A portable device including a biometric voice sensor configured to detect voice information and to take an action in response to speech spoken into the voice sensor. The device also includes a voice processor configured to process the voice sensor signal characteristics. The portable device may encrypt the detected signal and may compare the detected signal characteristics with voice characteristics that are stored in a memory of the portable device for applications such as voice enabled authentication, identification, command execution, encryption, and free speech recognition. The voice sensor may include a thin membrane portion that detects pressure waves caused by human speech. The portable device may be a contact-type smart card, a contactless smart card, or a hybrid smart card with contact and contactless interfaces. The device may be powered by an internal battery or by a host via contacts or by a power signal making use of the antenna in a contactless implementation.

Abstract: A chip for a chip-incorporating portable article having a card format, such as for smartcards. The chip includes a silicon substrate layer having integrated circuits in its active face defining a central processor unit and memories. The chip also includes physical means for providing physical protection against the action of electromagnetic radiation in the infrared range of wavelength longer than 1 ?m.

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: A two-way communication device has a master transmitter (SysM1, TRM1, SysM2, TRM2) connected to at least one slave transmitter (SysS1, TRS1, SysS2, TRS2) by an active connection wire. The master transmitter and the slave transmitter have a common reference (GND). The master transmitter can transmit a master signal (S1) to the slave transmitter and the slave transmitter can transmit a slave signal (S2) to the master transmitter. The master signal (S1) is a digital modulation in voltage. The slave signal (S2) is a digital modulation in current.

Abstract: A sealing-object (4) is fixed to a base-object (10). The sealing-object comprises a through-hole (5). The objects are fixed to each other in the following manner. In a preparation step, a fixing layer (1, 2, 3) is provided between the base-object and the sealing-object. In addition an evacuation device (6) equipped with an evacuation channel (7) is placed onto the sealing-object. The through-hole of the sealing object has a first extremity opening out on the evacuation channel and a second extremity opening out on the fixing layer. In a fixing step, the fixing layer is heated which causes the fixing layer to release gas. The gas is at least partially evacuated via the through-hole of the sealing-object and the evacuation channel of the evacuation device.

Abstract: A plurality of assemblies is manufactured. Each assembly comprises a sealing slice that is fixed to a base slice. The plurality of assemblies is manufactured in the following manner. In a preparation step, a stack is formed. The stack comprises a plurality of pre-assemblies. Each pre-assembly comprises a base slice, a sealing slice and a fixing layer provided between the base slice and the sealing slice. The stack further comprises at least one supple buffer layer. The supple buffer layer has a mechanical rigidity, which is substantially less than that of the base slices and that of the sealing slices. The supple buffer layer thus enables to compensate for variations in thickness of the base slices and of the sealing slices. In a fixing step, the stack is pressed which causes the sealing slice of each pre-assembly to be fixed to the base-slice of the pre-assembly.

Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract: A sealing-object (4) is fixed to a base-object (10). The sealing-object comprises a through-hole (5). The objects are fixed to each other in the following manner. In a preparation step, a fixing layer (1, 2, 3) is provided between the base-object and the sealing-object. In addition an evacuation device (6) equipped with an evacuation channel (7) is placed onto the sealing-object. The through-hole of the sealing object has a first extremity opening out on the evacuation channel and a second extremity opening out on the fixing layer. In a fixing step, the fixing layer is heated which causes the fixing layer to release gas. The gas is at least partially evacuated via the through-hole of the sealing-object and the evacuation channel of the evacuation device.

Abstract: The invention concerns a microcontroller (30) intended to be incorporated in a portable object (1) of type smartcard, including at least: a contact stud (VCC) to supply the said microcontroller (30) with current; a data input and/or output contact stud (I/O); an efficient data processing part (?CE); and confidential information. According to the invention, the microcontroller also includes: means (GEN, CAP, COM) to vary the supply voltage of the efficient data processing part (?CE), the said means being able to secure the said confidential data against current attacks.