Patents by Inventor Robert Lindsey BRISTOL

Robert Lindsey BRISTOL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157619
    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
    Type: Application
    Filed: February 3, 2022
    Publication date: May 19, 2022
    Inventors: Kevin LIN, Robert Lindsey BRISTOL, Alan M. MYERS
  • Patent number: 11276581
    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert Lindsey Bristol, Alan M. Myers
  • Patent number: 10692757
    Abstract: Embodiments of the invention include photoresist materials and methods of patterning photoresist materials. In an embodiment a photoresist material comprises a plurality of molecular glasses (MGs). In an embodiment, a glass transition temperature Tg of the photoresist material is less than an activation temperature needed to deblock blocking groups from the MGs. Embodiments include a method of patterning a photoresist material that comprises exposing the photoresist material with ultraviolet radiation. The method may also comprise, performing a first post exposure bake at a first temperature, that is less than the activation temperature needed to deblock blocking groups from the MGs, and performing a second post exposure bake at a second temperature that is approximately equal to or greater than the activation temperature needed to deblock blocking groups from the MGs.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Marie Krysak, Robert Lindsey Bristol, Paul Anton Nyhus, Michael J. Leeson
  • Patent number: 10593627
    Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Kanwal Jit Singh, Kevin Lin, Robert Lindsey Bristol
  • Publication number: 20190287813
    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Inventors: Kevin LIN, Robert Lindsey BRISTOL, Alan M. MYERS
  • Patent number: 10366950
    Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert Lindsey Bristol, James M. Blackwell, Rami Hourani
  • Patent number: 10366903
    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert Lindsey Bristol, Alan M. Myers
  • Publication number: 20180204797
    Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.
    Type: Application
    Filed: June 26, 2015
    Publication date: July 19, 2018
    Inventors: Kevin LIN, Robert Lindsey BRISTOL, James M. BLACKWELL, Rami HOURANI
  • Publication number: 20180158694
    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 7, 2018
    Inventors: Kevin LIN, Robert Lindsey BRISTOL, Alan M. MYERS
  • Publication number: 20180145035
    Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.
    Type: Application
    Filed: June 25, 2015
    Publication date: May 24, 2018
    Inventors: Kanwal Jit SINGH, Kevin LIN, Robert Lindsey BRISTOL
  • Publication number: 20180102282
    Abstract: Embodiments of the invention include photoresist materials and methods of patterning photoresist materials. In an embodiment a photoresist material comprises a plurality of molecular glasses (MGs). In an embodiment, a glass transition temperature Tg of the photoresist material is less than an activation temperature needed to deblock blocking groups from the MGs. Embodiments include a method of patterning a photoresist material that comprises exposing the photoresist material with ultraviolet radiation. The method may also comprise, performing a first post exposure bake at a first temperature, that is less than the activation temperature needed to deblock blocking groups from the MGs, and performing a second post exposure bake at a second temperature that is approximately equal to or greater than the activation temperature needed to deblock blocking groups from the MGs.
    Type: Application
    Filed: May 28, 2015
    Publication date: April 12, 2018
    Inventors: Marie KRYSAK, Robert Lindsey BRISTOL, Paul Anton NYHUS, Michael J. LEESON