Abstract: Several methods for reducing the occurrence of masking of errors when using "Cross-Check" integrated circuit testing arrays and data compression devices such as multiple input shift registers are disclosed. The methods reduce the probability that successive faults within the logic circuit nodes of the integrated circuit will cancel one another by insuring that signals from logically proximate circuit nodes are either not provided sequentially to the data compression circuitry or are provided in such a way as to store any given error in at least two different locations.

Abstract: Methods for fashioning CrossCheck testing structures allow the testing of high density integrated circuit structures to be made in a space efficient manner. In one method, sense lines and probe lines are disposed in different layers perpendicular to one another and a diffusion line is overlaid in such a manner as to form a sense transistor. In another method, a pair of probe lines are routed between each pair of cells in a manner to form a sense transistor. In still another embodiment circuit layout requires no modification to the basic macrocell structure and a metal interconnection layer is used to couple sense transistors to individual cells.

Abstract: A gate array layout in which alternative rows include areas of devices of the same diffusion type, and all the rows run in parallel on the device. However, the diffusion areas in adjacent rows are offset with respect to one another so that only cells in alternative rows which are all of one conductivity define straight parallel columns. By providing this relative offset between adjacent rows, the contacts to the source, drain and gate of interconnected devices all lie on straight lines, thereby simplifying the metal interconnect patterns. In addition to cells along each row being immediately abutting, cells in adjacent rows are abutting (although offset with respect to each other) so that no routing channels need be reserved.