Abstract: A display system (100) includes a memory (102) storing a set of pixel performance data entries including a first entry (104-1) associated with a first performance level of a first pixel and a second entry (104-2) associated with a second performance level of a second pixel. The display system further includes a first pixel driver (106) configured to drive the first pixel (108-1) at a first drive strength selected, based on the first entry, from a first plurality of drive strengths available to the first pixel driver. The display system also includes a second pixel driver (106) configured to drive the second pixel (108-2) at a second drive strength selected, based on the second entry, from a second plurality of drive strengths available to the second pixel driver. In a case where the second performance level is higher than the first performance level (116), the second drive strength is lower than the first drive strength (114).

Abstract: A display system may include a segment analyzer, a segment buffer, and a set of pixel drivers. The segment analyzer may perform an analysis of image data representing an image to be displayed. The analysis distinguishes a first portion of the image data that corresponds to an active segment of the image containing non-zero content from a second portion of the image data that corresponds to an empty segment of the image without non-zero content. The segment buffer stores the first portion of the image data in accordance with a segment map based on the analysis. The pixel drivers then use the segment map and the image data to cause a set of pixels to display the image by driving a first subset of pixels associated with the active segment without driving a second subset of pixels associated with the empty segment.

Abstract: A display system (100) includes a memory (102) storing a set of pixel performance data entries including a first entry (104-1) associated with a first performance level of a first pixel and a second entry (104-2) associated with a second performance level of a second pixel. The display system further includes a first pixel driver (106) configured to drive the first pixel (108-1) at a first drive strength selected, based on the first entry, from a first plurality of drive strengths available to the first pixel driver. The display system also includes a second pixel driver (106) configured to drive the second pixel (108-2) at a second drive strength selected, based on the second entry, from a second plurality of drive strengths available to the second pixel driver. In a case where the second performance level is higher than the first performance level (116), the second drive strength is lower than the first drive strength (114).

Abstract: An illustrative display system includes an array of pixels and a frame controller configured to cause the array of pixels to display an image frame by performing a series of successive field updates. The series of successive field updates includes a first field update in which a first write pointer circuit tracks a first traversal, during a first update period, across the array of pixels to update the array of pixels from a first to a second image field in the sequence, and a second field update in which a second write pointer circuit tracks a second traversal, during a second update period, across the array of pixels to update the array of pixels from the second to a third image field in the sequence. The second update period of the second field update overlaps the first update period of the first field update.

Abstract: A backplane operative to drive an array of emissive pixel elements forming a part of an automotive head lamp assembly is disclosed. Each pixel element comprises a memory cell operative to pulse width modulate a current mirror pixel drive circuit configured to drive an emissive element. The array of emissive pixel elements is divided into a plurality of interdigitated rows or columns serviced by independent row drivers or independent column drivers that may be driven by data selected to randomize the order in which the data on adjacent pixels of the same row are written, thereby effectively substantially reducing the visibility of any residual structures that may be present in the data driving the pixels of adjacent columns.

Abstract: A backplane for driving a display includes a two-dimensional array of pixel drive circuits, organized as a plurality of rows and a plurality of columns. The backplane has at least one shift register addressing assembly that includes a shift register chain formed of a plurality of controlling shift registers serially connected with, and separated by, equal sized groups of non-controlling shift registers. Each controlling shift register controls a different one of a plurality of word lines that each connect with pixel drive circuits of one row. The backplane also includes a plurality of bit lines that each connect with pixel drive circuits of one column. A shift register data sequence is input to a first one of the plurality of controlling shift registers and propagates through the shift register chain to control the plurality of word lines to load display values from the bit lines into the pixel drive circuits.

Abstract: A backplane operative to drive an array of emissive pixel elements forming a part of an automotive head lamp assembly is disclosed. Each pixel element comprises a memory cell operative to pulse width modulate a current mirror pixel drive circuit configured to drive an emissive element. The array of emissive pixel elements is divided into a plurality of interdigitated rows or columns serviced by independent row drivers or independent column drivers that may be driven by data selected to randomize the order in which the data on adjacent pixels of the same row are written, thereby effectively substantially reducing the visibility of any residual structures that may be present in the data driving the pixels of adjacent columns.

Abstract: A backplane operative to drive an array of emissive pixel elements forming a part of an automotive head lamp assembly is disclosed. Each pixel element comprises a memory cell operative to pulse width modulate a current mirror pixel drive circuit configured to drive an emissive element. The array of emissive pixel elements is divided into a plurality of interdigitated rows or columns serviced by independent row drivers or independent column drivers that may be driven by data selected to randomize the order in which the data on adjacent pixels of the same row are written, thereby effectively substantially reducing the visibility of any residual structures that may be present in the data driving the pixels of adjacent columns.

Abstract: A backplane for driving a display includes a two-dimensional array of pixel drive circuits, organized as a plurality of rows and a plurality of columns. The backplane has at least one shift register addressing assembly that includes a shift register chain formed of a plurality of controlling shift registers serially connected with, and separated by, equal sized groups of non-controlling shift registers. Each controlling shift register controls a different one of a plurality of word lines that each connect with pixel drive circuits of one row. The backplane also includes a plurality of bit lines that each connect with pixel drive circuits of one column. A shift register data sequence is input to a first one of the plurality of controlling shift registers and propagates through the shift register chain to control the plurality of word lines to load display values from the bit lines into the pixel drive circuits.

Abstract: A method for providing gray scale for an array of current emissive devices sensitive to the current level driving them, such as an LEDs, is disclosed. Multiple current sources are operated in parallel for each emissive device with the on/off state of each of the multiple current source controlled by a memory circuit. Means for pulse width modulating the array of current sensitive devices to enable greater control over gray scale is presented.

Abstract: A backplane operative to drive an array of emissive pixel elements forming a part of an automotive head lamp assembly is disclosed. Each pixel element comprises a memory cell operative to pulse width modulate a current mirror pixel drive circuit configured to drive an emissive element. The array of emissive pixel elements is divided into a plurality of interdigitated rows or columns serviced by independent row drivers or independent column drivers that may be driven by data selected to randomize the order in which the data on adjacent pixels of the same row are written, thereby effectively substantially reducing the visibility of any residual structures that may be present in the data driving the pixels of adjacent columns.

Abstract: A method of pulse width modulating a spatial light modulator comprises determining a modulation sequence and applying the modulation sequence to the spatial light modulator in a time order method. The modulation sequence comprises a plurality of minor modulation segments. Each minor modulation segment comprises an always-on modulation segment in an always-on state. The plurality of minor modulation segments are temporally spaced such that the always-on modulation segments are spaced at predetermined intervals. Each minor modulation segment comprises at least one thermometer bit.

Abstract: A method of organizing and ordering pulse width modulation image data is disclosed, so that it may be displayed on the pixels of a scrolling color display. The method includes a method of formatting received image data into a different form suitable for driving a pulse width modulated display and a method of distributing image data across a series of different image modulation segments to minimize flicker and gray scale errors. The method includes means for reducing lateral field effects between adjacent pixels in different data states.

Abstract: The present application provides a method of pulse width modulating a spatial light modulator. The method comprises determining a modulation sequence and applying said modulation sequence to said spatial light modulator in a time order method. Said modulation sequence comprises a plurality of minor modulation segments. Each minor modulation segment comprises an “always on” modulation segment in an “always on” state. Said plurality of minor modulation segments are temporally spaced such that said “always on” modulation segments are spaced at predetermined intervals. Each minor modulation segment comprises at least one thermometer bit.

Abstract: A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell.

Abstract: A method of organizing and ordering pulse width modulation image data is disclosed, so that it may be displayed on the pixels of a scrolling color display. The method includes a method of formatting received image data into a different form suitable for driving a pulse width modulated display and a method of distributing image data across a series of different image modulation segments to minimize flicker and gray scale errors. The method includes means for reducing lateral field effects between adjacent pixels in different data states.

Abstract: A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell.

Abstract: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.

Abstract: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.

Abstract: A shining fan structure for displaying images of patterns or characters by reflection mainly includes a fan. A plurality of blades of the fan are provided with reflective patterns or characters. Light-emitting elements are provided on the periphery of the fan base. Each light-emitting element is angled to directly irradiate the front of the blade. When the fan rotates, the light-emitting elements provided on the periphery of the base irradiate the patterns or characters provided on the blades with the lightening frequency being synchronous with or different from the rotation speed of the fan, a shining effect can be seen from the front or side of the fan by reflection or transmission.