Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

Abstract: A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.

Abstract: A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.