Patents by Inventor Robert M. Biglow

Robert M. Biglow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process and apparatus for characterizing intellectual property for integration into an IC platform environment
    Patent number: 7103858
    Abstract: A footprint based optimal characterization of intellectual property (IP) for more deterministic physical integration. The physical integration characteristics are based upon IP physical integration at an anchor point in a pre-defined IC platform. IP footprint characteristics are identified as fixed, variable or prioritized to each other, and bounding constraints are defined based on a set of characteristics for the IP, the platform characteristics and IC design requirements. The IP is physically synthesized using the bounding constraints. The synthesized IP is tested and the bounding constraints are iteratively modified until the characteristics of the synthesized IP are optimized/captured.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: September 5, 2006
    Assignee: LSI Logic Corporation
    Inventors: Jonathan W. Byrn, Robert M. Biglow