Abstract: A circuit for emulating bit-level erasable non-volatile memory includes an emulator that activates a first virtual sector of a bit-level programmable, block-level erasable non-volatile memory. The first virtual sector receives and stores write requests having an address and a record to be written to the received address. A linked list of records is used to store each subsequent record received in subsequent write requests having the received address. A separate thread in the linked list is maintained for each different received address. The last record subsequently received for each of the received addresses is copied to a linked list of a second virtual sector when a first operating parameter has been exceeded. The active virtual sector is deactivated and erased when the last record subsequently received for each of the received addresses in the linked list of the active virtual sector have been copied to the second virtual sector.

Abstract: A circuit for emulating bit-level erasable non-volatile memory includes an emulator that activates a first virtual sector of a bit-level programmable, block-level erasable non-volatile memory. The first virtual sector receives and stores write requests having an address and a record to be written to the received address. A linked list of records is used to store each subsequent record received in subsequent write requests having the received address. A separate thread in the linked list is maintained for each different received address. The last record subsequently received for each of the received addresses is copied to a linked list of a second virtual sector when a first operating parameter has been exceeded. The active virtual sector is deactivated and erased when the last record subsequently received for each of the received addresses in the linked list of the active virtual sector have been copied to the second virtual sector.

Abstract: In a non-volatile memory unit such as a flash memory unit, the degradation of charge can result in an error during a read operation. By using the error checking and correction techniques, a determination can be made whether a detected error can be corrected and, if correctable, is the consistent with charge degradation at that bit position displaying the error. When a correctable error is detected, the signal group address and the correction pattern are stored and an interrupt request flag applied to the central processing unit. When the interrupt flag is processed, the central processing unit, using the signal group address and the correction pattern, restores the charge of the bit position in the memory unit. In this manner, further read operations involving the restored bit position will not repeat the corrected error.

Abstract: In a non-volatile memory unit such as a flash memory unit, the degradation of charge can result in an error during a read operation. By using the error checking and correction techniques, a determination can be made whether a detected error can be corrected and, if correctable, is the consistent with charge degradation at that bit position displaying the error. When a correctable error is detected, the signal group address and the correction pattern are stored and an interrupt request flag applied to the central processing unit. When the interrupt flag is processed, the central processing unit, using the signal group address and the correction pattern, restores the charge of the bit position in the memory unit. In this manner, further read operations involving the restored bit position will not repeat the corrected error.

Abstract: In a Flash memory unit, the storage of a logic signal in the memory cells is determined by performing a READ operation. The NORMAL READ operation requires that the floating gate store an amount of charge QNR above which a logic “0” is identified and below which a logic “1” is identified as being stored in the memory cell. A second level of charge QTR stored on the floating gate is used in a TEST READ operation. The stored charge QTR is greater than the stored charge QNR, but less than the charge stored on the floating gate as the result of a WRITE operation. The result of a TEST READ operation is compared with a NORMAL READ operation of a memory cell. When the logic state identified by the TEST READ operation and the NORMAL READ operation are not the same, the charge on the cell is determined to have decayed below a prescribed level and the memory cell is refreshed to the level that is present during a WRITE operation.

Abstract: In a Flash memory unit, the storage of a logic signal in the memory cells is determined by performing a READ operation. The NORMAL READ operation requires that the floating gate store an amount of charge QNR above which a logic “0” is identified and below which a logic “1” is identified as being stored in the memory cell. A second level of charge QTR stored on the floating gate is used in a TEST READ operation. The stored charge QTR is greater than the stored charge QNR, but less than the charge stored on the floating gate as the result of a WRITE operation. The result of a TEST READ operation is compared with a NORMAL READ operation of a memory cell. When the logic state identified by the TEST READ operation and the NORMAL READ operation are not the same, the charge on the cell is determined to have decayed below a prescribed level and the memory cell is refreshed to the level that is present during a WRITE operation.

Abstract: A non-volatile counter memory is provided by using a gray code scale to store counter values in a plurality of counter memories (34) comprising a counter memory group (38). Each counter memory comprises a plurality of units which store a gray coded value. The weighting of the units is changed after a predetermined number of write operations such that the number of bit transitions is spread out among the units.