Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop (32) and locally oxidizing a P-doped silicon substrate (21) to define a collector region, implanting an N-type collector (43) and diffusing the implants (40, 44). Device emitter, collector and base contact features (64, 66, 68) are photolithographically defined by two openings (54, 56) spaced lengthwise along the collector region. Low resistivity P- and N-type regions (74, 80) are implanted in the substrate in the openings and covered by local oxidation (86, 88). The collector region is preferably formed in a keyhole shape with a wide collector contact feature (66B) and adjoining region 80B and narrow base contact (68B) and emitter (64B) features and intervening region (74B). The substrate (22) is exposed in the emitter and contact features. A single polysilicon layer (94) is deposited, selectively doped and oxidized to form separate base, collector and emitter contacts (94) and a triple diffused NPN transistor (116, 92, 40).

Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a collector region. An N-type collector is implanted and the implants are diffused to form a shallow gradient P-N junction. Then, device emitter, base and collector contact features are photolithographically defined by two openings spaced along the length of the collector region. The collector region is formed in a keyhole shape with a wider end portion encompassed by the collector contact feature and adjoining opening and a narrower opposite end portion which includes the base contact and emitter features and intervening opening. Low resistivity P- and N-type regions are implanted in the substrate in the openings; the openings are covered by local oxidation; and the substrate surface region are exposed in the adjoining contact features.