Abstract: A system includes a plurality of thermostats corresponding to a plurality of HVAC systems that serve a plurality of spaces and a computing system communicable with the plurality of thermostats via a network. The computing system is configured to, for each space of the plurality of spaces, obtain a set of training data relating to thermal behavior of the space, identify a model of thermal behavior of the space based on the set of training data, perform a model predictive control process using the model of thermal behavior of the space to obtain a temperature setpoint for the space, and provide the temperature setpoint to the thermostat corresponding to the HVAC system serving the space. The plurality of thermostats are configured to control the plurality of HVAC systems in accordance with the temperature setpoints.

Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.

Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.

Abstract: A tool comparing different health insurance plans. A User can review a plurality of health plans for likely cost, quality, and provider availability. The results are arranged in a table according to selectable criteria, such as actuarially estimated total costs (premiums plus actuarial estimate of out-of-pocket). Actuarial cost estimates are used with one or more of the following: personalized summary quality measures produced by the User's applying personal weights to different aspects of quality; availability of User-selected health care providers indicating if these providers participate in each listed plan; information on the costs and quality of available health care providers; ability for User to adjust actuarial estimates based on User-predicted health care conditions, procedures, and products; and ability for User to adjust premiums based on User preference as to whether to accept the full available subsidy. User can sort, filter, and select plans based on displayed features.

Abstract: A tool comparing different health insurance plans. A User can review a plurality of health plans for likely cost, quality, and provider availability. The results are arranged in a table according to selectable criteria, such as actuarially estimated total costs (premiums plus actuarial estimate of out-of-pocket). Actuarial cost estimates are used with one or more of the following: personalized summary quality measures produced by the User's applying personal weights to different aspects of quality; availability of User-selected health care providers indicating if these providers participate in each listed plan; information on the costs and quality of available health care providers; ability for User to adjust actuarial estimates based on User-predicted health care conditions, procedures, and products; and ability for User to adjust premiums based on User preference as to whether to accept the full available subsidy. User can sort, filter, and select plans based on displayed features.

Abstract: Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived clocking architecture by tracking the number of data transitions on inbound and outbound data lanes to make sure the minimum number of transitions occur. Other embodiments of the invention perform data inversions to increase the likelihood of meeting the minimum data transition density. Still other embodiments are described in the claims.

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract: Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Abstract: Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

Abstract: A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.

Abstract: Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract: Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.

Abstract: A method and circuit are provided for asynchronously loading data in a first data buffer and a second data buffer and synchronously reading the data from the first data buffer and the second data buffer. A load data circuit may receive a plurality of input signals and output a first latch enable signal and a second latch enable signal. The load data circuit may asynchronously operate based on the input signals. The first latch enable signal may enable data to be loaded in the first data buffer and the second latch enable signal may enable data to be loaded in the second data buffer. A read data circuit may be coupled to the first data buffer and the second data buffer. The read data circuit may synchronously address the first data buffer and said second data buffer so as to read the data based on a synchronous clock signal.