Abstract: A method for the fabrication of a double-sided electrical interconnection flexible circuit (200) particularly useful as a substrate for an area array integrated circuit package. A copper matrix with studs (203) is pressed through a dielectric film (201) having a copper layer on the opposite surface, thereby forming an intermediate structure for a flex circuit with self-aligned solid copper vias in a one step process. The contacts are reinforced by plating both surfaces with a layer of copper, and conventional processes are used to complete the circuit patterning.

Abstract: A lead frame including a first set of leads in a first plane and a second set of leads in a second plane offset vertically from the second plane. The leads in the first and second planes are offset from each other by a lead width.

Abstract: A method of fabricating a lead frame. The method includes providing an electrically conductive layer having a pair of opposing major surfaces. A pattern is etched in the layer extending partially through the layer to form cavities with sidewalls in the layer. A patterned mask is provided on the etched layer including masking of the sidewalls. The layer is again etched within the cavities. The patterned mask is preferably a liquid photo resist and the electrically conductive layer is preferably one of a copper or copper-based material or ALLOY 42. The etch can take place from both major surfaces.

Abstract: The invention is a lead frame that has leads formed in two levels during the etching process in which the lead frame is formed. A lead frame form (40), or continuous strip of lead frame material, is coated on two sides with a photo resist material (41,43). Each photo resist coated side is patterned to define leads on the lead frame. The lead patterns (41,43, 42,44) on the two sides are offset from each other so that patterns on one side of the lead frame material alternate with the patterns on the other side of the lead frame material. Both sides of the photo resist patterned lead frame material are etched to a depth exceeding the thickness of a lead. The photo resist (41,43) material is then removed. The resulting lead frame has leads (50-56) that are in two levels, each level having leads offset by a lead width from the other level, but with an effective zero distance between leads horizontally.

Abstract: The invention is a lead frame that has leads formed in two levels during the etching process in which the lead frame is formed. A lead frame form (40), or continuous strip of lead frame material, is coated on two sides with a photo resist material (41,43). Each photo resist coated side is patterned to define leads on the lead frame. The lead patterns (41,43, 42,44) on the two sides are offset from each other so that patterns on one side of the lead frame material alternate with the patterns on the other side of the lead frame material. Both sides of the photo resist patterned lead frame material are etched to a depth exceeding the thickness of a lead. The photo resist (41,43) material is then removed. The resulting lead frame has leads (50-56)that are in two levels, each level having leads offset by a lead width from the other level, but with an effective zero distance between leads horizontally.

Abstract: The invention is a method of forming the art work for chemically etching that produces uniform through-etch and lateral-etch. The artwork that defines the pattern to be etched utilizes lines equal to the narrowest feature that is to be etched. Rather than etch away large areas, section are removed by etching by cutting them out of the material that is being etched. The artwork or pattern is designed with the same compensation factors throughout the entire pattern and the etch rate will be completely uniform for the entire pattern.

Abstract: A double-sides electrical interconnection flexible circuit particularly useful as a substrate for an area array integrated circuit package is described. A circuit having interconnection patterns on one surface and solder ball contact pads on the second surface are interconnected by solid copper vias formed from an array of raised studs etched from a metal matrix. In reel to reel format, the etched metal matrix is adhered to one surface of the film and forms the base metal for the solder ball contact pads. The matrix with studs are presses through the dielectric film with a copper layer on the opposite surface, thereby forming an intermediate structure for a flex circuit with self-aligned solid copper vias in a one step process. The contacts are reinforced by plating both surfaces with a layer of copper, and conventional processes are used to complete the circuit patterning.

Abstract: A lead frame is plated with palladium and then selected portions of the lead frame leads are spot plated with silver to improve solderability.

Abstract: A lead frame is plated with palladium and then selected portions of the lead frame leads are spot plated with silver to improve solderability.

Abstract: The invention is to a method of spot plating parts of a plated semiconductor lead frame. The entire lead frame is first plated. Then parts of the lead frame, internal to the subsequent encapsulating package, are spot plated prior to encapsulating the semiconductor device. A spot of silver is plated in the mount and/or bond area of the lead frame.