Patents by Inventor Robert M. Glidden

Robert M. Glidden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RFID tag with bist circuits
    Patent number: 7380190
    Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: May 27, 2008
    Assignee: IMPINJ, Inc.
    Inventors: Dennis Kiyoshi Hara, Robert M. Glidden
  • Wafer level testing for RFID tags
    Patent number: 7312622
    Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: December 25, 2007
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Robert M. Glidden, Andrew Edward Horch, Jay A. Kuhn, Ronald A. Oliver
  • RFID tag design with circuitry for wafer level testing
    Patent number: 7307528
    Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: December 11, 2007
    Assignee: IMPINJ, Inc.
    Inventors: Robert M. Glidden, Dennis Kiyoshi Hara, Ronald A. Oliver, Jay A. Kuhn, John D. Hyde