Abstract: An image sensor may have a pixel array that includes an array of pixels arranged in rows and columns. Each pixel may include a number of adjacent sub-pixels covered by a single microlens. The adjacent sub-pixels of each pixel may include color filter elements of the same color. Image signals from the sub-pixels may be used to calculate phase information in each pixel in the array. This information may be used to generate a depth map of the entire captured image. The pixels may each be able to detect vertical, horizontal, or diagonal edges. Additionally, the image signals from each photodiode in a pixel may be binned or average to obtain image data for each pixel. The image sensor also may generate high-dynamic-range images using the pixel array.

Abstract: Image sensors may include an array of photodiodes arranged in groups of adjacent photodiodes that generate charge in response to same-colored light. The image sensor may generate high-dynamic-range (HDR) images. To establish an effective exposure ratio between sets of photodiodes on the array for generating HDR images, microlenses may be formed over some photodiodes in a checkerboard pattern and may have portions that extend over other photodiodes in the array. Control circuitry may control photodiodes in each group to perform pulsed integration in which charge transfer control signals are intermittently pulsed for those photodiodes. A substantially opaque element may be formed over photodiodes in each of the groups such that the corresponding photodiodes generate signals in response to crosstalk. In this way, different effective exposures may be established across the array, allowing for HDR images to be generated without motion artifacts and with super-pixel resolution.

Abstract: An image sensor may have a pixel array that includes an array of pixels arranged in rows and columns. Each pixel may include a number of adjacent sub-pixels covered by a single microlens. The adjacent sub-pixels of each pixel may include color filter elements of the same color. Image signals from the sub-pixels may be used to calculate phase information in each pixel in the array. This information may be used to generate a depth map of the entire captured image. The pixels may each be able to detect vertical, horizontal, or diagonal edges. Additionally, the image signals from each photodiode in a pixel may be binned or average to obtain image data for each pixel. The image sensor also may generate high-dynamic-range images using the pixel array.

Abstract: Image sensors may include an array of photodiodes arranged in groups of adjacent photodiodes that generate charge in response to same-colored light. The image sensor may generate high-dynamic-range (HDR) images. To establish an effective exposure ratio between sets of photodiodes on the array for generating HDR images, microlenses may be formed over some photodiodes in a checkerboard pattern and may have portions that extend over other photodiodes in the array. Control circuitry may control photodiodes in each group to perform pulsed integration in which charge transfer control signals are intermittently pulsed for those photodiodes. A substantially opaque element may be formed over photodiodes in each of the groups such that the corresponding photodiodes generate signals in response to crosstalk. In this way, different effective exposures may be established across the array, allowing for HDR images to be generated without motion artifacts and with super-pixel resolution.

Abstract: Methods, systems, and apparatuses provide dynamic creation and modification of wafer test maps. Test plans are defined for a testing session of a wafer lot. The test plan is associated with a number of seed map patterns. During a wafer lot testing session, test results are dynamically obtained and examined at run-time of a test. Moreover, the seed map patterns are overlaid on the test sites defined in the test plan. If the test result statistics are outside of defined threshold tolerance levels, then a new wafer test map is created or modified at run-time, according to corresponding seed map patterns. If seed map patterns are within the intersection of valid test sites, then seed map patterns are created at run-time.

Abstract: Methods, systems, and apparatuses provide dynamic creation and modification of wafer test maps. Test plans are defined for a testing session of a wafer lot. The test plan is associated with a number of seed map patterns. During a wafer lot testing session, test results are dynamically obtained and examined at run-time of a test. Moreover, the seed map patterns are overlaid on the test sites defined in the test plan. If the test result statistics are outside of defined threshold tolerance levels, then a new wafer test map is created or modified at run-time, according to corresponding seed map patterns. If seed map patterns are within the intersection of valid test sites, then seed map patterns are created at run-time.

Abstract: An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

Abstract: An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

Abstract: An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.