Abstract: A method and mechanism for error recovery in a processor. A multithreaded processor is configured to utilize software for hardware detected machine errors. Rather than correcting and clearing the detected errors, hardware is configured to report the errors precisely. Both program-related exceptions and hardware errors are detected and, without being corrected by the hardware, flow down the pipeline to a trap unit where they are prioritized and handled via software. The processor assigns each instruction a thread ID and error information as it follows the pipeline. The trap unit records the error by using the thread ID of the instruction and the pipelined error information in order to determine which ESR receives the information and what to store in the ESR. A trap handling routine is then initiated to facilitate error recovery.

Abstract: In an embodiment, the present invention describes a method and apparatus for detecting RAW condition earlier in an instruction pipeline. The store instructions are stored in a special store bypass buffer (SBB) within an instruction decode unit (IDU). The IDU compares the instruction fields that are used for address generation of all ‘load’ instructions against ‘store’ instructions within a group of fetched instructions and ‘store’ instructions previously stored in the SBB. If a match of instruction fields is found, the IDU ‘speculates’ that the load instruction has dependency on the ‘store’ instruction. A data cache unit (DCU) validates the dependency of the load instruction ‘speculated’ by the IDU. If a false dependency is ‘speculated’ by the IDU, the DCU forces a re-fetch of the load instruction.

Abstract: In a computer system including an interrupt processor for interrupting a program being processed by the computer system, a sub-system for processing interrupt requests to the interrupt processor. The sub-system comprises hardware circuit for generating hardware interrupt requests and control circuit for implementing control software where the control software causing software interrupt requests to be generated by said control circuit. An interrupt register stores and identifies both the hardware and software interrupt requests. A selection circuit selects and sends one of said stored interrupt request stored in the interrupt register to the interrupt processor for processing. The control circuit, under control of the control software, generates an end software interrupt requests for removing software interrupt request stored in the interrupt register such that software interrupt in the computer system can be generated and terminated under the control of the control software.

Abstract: A computer system having a chief system control program running in a real machine as a host where the host controls standard system control programs (SCP's) and controls virtual machines (Domains) called guests. Guests operate with interpretive execution as second-level guests. Control is transferred from a second-level guest to the guest SCP or to the chief SCP with only one control interception. Control is transferred directly between the second-level guest and the Chief SCP bypassing the first-level guest.

Abstract: In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.

Abstract: An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.

Abstract: An interlock of an instruction processing pipeline in a data processing system responsive to the validity of the pipeline stages within the instruction unit pipeline under microprogram control, is provided. Thus, a microprogram can provide for the release of a particular pipeline stage based on a selected characteristic of the valid signals generated by other stages of the pipeline. An interlock control signal is generated by a decode of a field in a microinstruction stored in a control store RAM or through hardwired decoding.

Abstract: The present invention provides for use in a data processor a method for mapping a respective machine language instruction stored by cache storage unit to a respective microprogrammed algorithm stored in control storage unit means, wherein the respective machine language instruction includes an opcode field with a prescribed value and at least one nonopcode field with one of a plurality of values, the method, comprising the steps of in the course of one data processor clock cycle, providing the respective machine language instruction to a decoder for converting the prescribed opcode field and the at least one nonopcode field of the respective machine language instruction into a respective combination of decoded signals which corresponds to the prescribed opcode field value and that at least one nonopcode field value of the respective machine language instruction; and providing the respective combination of decoded signals to combinational logic for converting the respective combination of decode signals into a

Abstract: In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.

Abstract: Disclosed is an error-tracking unit within a data processing system. Each data location to be checked for error and to be located in the case of an error is provided with error detection circuitry. Each data location is additionally provided with an error history register for storing an error signal. When the error-detecting circuit detects an error, the error history register is enabled to store the error signal. Whenever an error is detected, the error history registers are inhibited from further change so that errors are not propagated. The error detection also causes a machine check signal which, in general, prevents the data processing system from normal processing.