Patents by Inventor Robert M. Nickerson

Robert M. Nickerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THROUGH MOLD INTERCONNECT DRILL FEATURE
    Publication number: 20260190967
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.
    Type: Application
    Filed: February 19, 2026
    Publication date: July 2, 2026
    Inventors: Robert M. NICKERSON, Rees WINTERS, Purushotham Kaushik MUTHUR SRINATH
  • Through mold interconnect drill feature
    Patent number: 12604720
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: April 14, 2026
    Assignee: Intel Corporation
    Inventors: Robert M. Nickerson, Rees Winters, Purushotham Kaushik Muthur Srinath
  • OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON- PACKAGE STRUCTURES
    Publication number: 20260018579
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Application
    Filed: September 24, 2025
    Publication date: January 15, 2026
    Applicant: Intel Corporation
    Inventors: Russell K. MORTENSEN, Robert M. NICKERSON, Nicholas R. WATTS
  • MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE
    Publication number: 20250329604
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: July 1, 2025
    Publication date: October 23, 2025
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone
    Patent number: 12417958
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: September 16, 2025
    Assignee: Intel Corporation
    Inventors: Elizabeth Nofen, Shripad Gokhale, Nick Ross, Amram Eitan, Nisha Ananthakrishnan, Robert M. Nickerson, Purushotham Kaushik Muthur Srinath, Yang Guo, John C. Decker, Hsin-Yu Li
  • Through mold interconnect drill feature
    Patent number: 12406906
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: September 2, 2025
    Assignee: Intel Corporation
    Inventors: Robert M. Nickerson, Rees Winters, Purushotham Kaushik Muthur Srinath
  • Laser ablation-based surface property modification and contamination removal
    Patent number: 12394773
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: August 19, 2025
    Assignee: Intel Corporation
    Inventors: Denis Myasishchev, Andrew V. Mazur, Purushotham Kaushik Muthur Srinath, Robert M. Nickerson, Shripad Gokhale
  • Laser ablation-based surface property modification and contamination removal
    Patent number: 12362340
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 15, 2025
    Assignee: Intel Corporation
    Inventors: Denis Myasishchev, Andrew V. Mazur, Purushotham Kaushik Muthur Srinath, Robert M. Nickerson, Shripad Gokhale
  • Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone
    Patent number: 12347743
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: July 1, 2025
    Assignee: Intel Corporation
    Inventors: Elizabeth Nofen, Shripad Gokhale, Nick Ross, Amram Eitan, Nisha Ananthakrishnan, Robert M. Nickerson, Purushotham Kaushik Muthur Srinath, Yang Guo, John C. Decker, Hsin-Yu Li
  • Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone
    Patent number: 12315777
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 27, 2025
    Assignee: Intel Corporation
    Inventors: Elizabeth Nofen, Shripad Gokhale, Nick Ross, Amram Eitan, Nisha Ananthakrishnan, Robert M. Nickerson, Purushotham Kaushik Muthur Srinath, Yang Guo, John C. Decker, Hsin-Yu Li
  • Offset interposers for large-bottom packages and large-die package-on-package structures
    Patent number: 12107082
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON- PACKAGE STRUCTURES
    Publication number: 20240222350
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventors: Russell K. MORTENSEN, Robert M. NICKERSON, Nicholas R. WATTS
  • Offset interposers for large-bottom packages and large-die package-on-package structures
    Patent number: 11978730
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE
    Publication number: 20240128152
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • LASER ABLATION-BASED SURFACE PROPERTY MODIFICATION AND CONTAMINATION REMOVAL
    Publication number: 20240128253
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Denis MYASISHCHEV, Andrew V. MAZUR, Purushotham Kaushik MUTHUR SRINATH, Robert M. NICKERSON, Shripad GOKHALE
  • MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE
    Publication number: 20240021493
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • THROUGH MOLD INTERCONNECT DRILL FEATURE
    Publication number: 20240021500
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Inventors: Robert M. NICKERSON, Rees WINTERS, Purushotham Kaushik MUTHUR SRINATH
  • MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE
    Publication number: 20240014097
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES
    Publication number: 20240006401
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Application
    Filed: September 14, 2023
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Russell K. MORTENSEN, Robert M. NICKERSON, Nicholas R. WATTS
  • Offset interposers for large-bottom packages and large-die package-on-package structures
    Patent number: 11798932
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts