Patents by Inventor Robert M. Nickerson

Robert M. Nickerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11056466
    Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Christopher L. Rumer, Nitin Deshpande, Robert M. Nickerson
  • Publication number: 20210066155
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20210066167
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventors: Robert M. NICKERSON, Rees WINTERS, Purushotham Kaushik MUTHUR SRINATH
  • Publication number: 20210066273
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Denis MYASISHCHEV, Andrew V. MAZUR, Purushotham Kaushik MUTHUR SRINATH, Robert M. NICKERSON, Shripad GOKHALE
  • Patent number: 10607976
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Publication number: 20190385983
    Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.
    Type: Application
    Filed: August 27, 2019
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: OMKAR KARHADE, CHRISTOPHER L. RUMER, NITIN DESHPANDE, ROBERT M. NICKERSON
  • Patent number: 10446530
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Patent number: 10438930
    Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Christopher L. Rumer, Nitin Deshpande, Robert M. Nickerson
  • Publication number: 20190103385
    Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Intel Corporation
    Inventors: OMKAR KARHADE, ROBERT L. SANKMAN, NITIN A. DESHPANDE, MITUL MODI, THOMAS J. DE BONIS, ROBERT M. NICKERSON, ZHIMIN WAN, HAIFA HARIRI, SRI CHAITRA J. CHAVALI, NAZMIYE ACIKGOZ AKBAY, FADI Y. HAFEZ, CHRISTOPHER L. RUMER
  • Publication number: 20190006319
    Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: OMKAR KARHADE, CHRISTOPHER L. RUMER, NITIN DESHPANDE, ROBERT M. NICKERSON
  • Patent number: 10128225
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
  • Patent number: 10121722
    Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Chandra M. Jha, Eric J. Li, Zhaozhi Li, Robert M. Nickerson
  • Publication number: 20170229438
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: February 17, 2017
    Publication date: August 10, 2017
    Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
  • Patent number: 9691727
    Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Javier Soto Gonzalez, Charavana K. Gurumurthy, Robert M. Nickerson, Debendra Mallik
  • Patent number: 9691728
    Abstract: An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Robert M. Nickerson, Min Tao, John S. Guzek
  • Patent number: 9613934
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 4, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
  • Publication number: 20160218093
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Application
    Filed: March 31, 2016
    Publication date: July 28, 2016
    Applicant: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Publication number: 20160133557
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Application
    Filed: December 24, 2015
    Publication date: May 12, 2016
    Applicant: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Publication number: 20150221608
    Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Applicant: Intel Corporation
    Inventors: Javier SOTO GONZALEZ, Charavana K. GURUMURTHY, Robert M. NICKERSON, Debendra MALLIK
  • Publication number: 20150171044
    Abstract: An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Inventors: Robert M. NICKERSON, Min TAO, John S. GUZEK