Abstract: A portable insect control trap has, in a single portable device, two modes of attracting insects, including a first mode adapted to attract flying insects (e.g. insect-attracting light) and a second mode adapted to attract crawling insects (e.g., bait). The same device has two modes of killing insects, including a first mode adapted to kill flying insects (e.g. an electrified grid) and a second mode adapted to kill crawling insects (e.g. an electric heating element). The first mode of attracting is associated with the first mode of killing, the second mode of attracting is associated with the second mode of killing.

Abstract: An apparatus and method for automatically controlling rotation of a transducer that is mechanically coupled to a motor are disclosed. The apparatus includes a motor controller coupled to the motor and a microprocessor. The motor controller includes a state-machine and an encoder. The microprocessor is coupled to the state-machine. Two methods for automatically controlling rotation of an ultrasound transducer are disclosed. The first method includes the steps of providing a microprocessor coupled to a motor controller, the motor controller comprising a state-machine and a speed setting circuit, and initializing the state-machine by providing a desired speed and a target position from the microprocessor. The first method further includes the step of automatically selecting the desired speed from the speed setting circuit in accordance with the initialized state-machine. The first method further includes rotating the ultrasound transducer at the selected speed.

Abstract: A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

Abstract: A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

Abstract: A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.