Abstract: A support chip includes substantially all the AT core logic, namely most of the X-bus peripherals (except for the keyboard controller), memory controllers, and swapper. The normal AT data paths are altered to reduce the pin count, with a resulting surprising improvement in capability. The chip interfaces to the microprocessor's local address and data buses and provides a 16-bit data bus corresponding to a 16-bit version of the X-bus data portion (XD-bus). External buffers coupled to the XD-bus provide a system data bus (SD-bus) corresponding to the S-bus data portion. The I/O channel is coupled to the SD-bus while system ROM is coupled to the XD-bus. To accommodate the fact that the swapper is internal, the support chip provides independent direction control of the high and low order buffers between the XD-bus and the SD-bus.

Abstract: The present invention provides a contrast enhancing method and circuit for mapping color signals into signals for driving a display which is capable of displaying shades of gray. With the present invention a preliminary translation is first made between a foreground-background color combination and the various shades of gray that can be displayed. The contrast or separation between the foreground level of gray and the background level of gray produced by this preliminary translation is then compared to parameters set by the operator.

Abstract: A single semiconductor chip containing both I/O bus controller and DRAM controller functions. A single pin on the chip is used to provide both a zero wait state input to the I/O bus controller and to provide a local bus access (LBA) signal for inhibiting both the I/O bus controller and the DRAM controller when an external device is doing an I/O or memory operation on the local bus. Logic isprovided to produce an inhibit signal to the I/O bus controller in response to the LBA signal. Another logic circuit is provided to inhibit the DRAM controller in response to the LBA signal only when there is a memory cycle signal from the microprocessor. The use of the single pin is possible since the zero wait state isgnal will only appear during the latter part of an I/O or memory cycle, which is mutually exclusive with the start of an I/O or memory cycle, which is the only time the LBA signal will appear.

Abstract: A support chip includes substantially all the AT core logic, namely most of the X-bus peripherals (except for the keyboard controller), memory controllers, and swapper. The normal AT data paths are altered to reduce the pin count, with a resulting surprising improvement in capability. The chip interfaces to the microprocessor's local address and data buses and provides a 16-bit data bus corresponding to a 16-bit version of the X-bus data portion (XD-bus). External buffers coupled to the XD-bus provide a system data bus (SD-bus) corresponding to the S-bus data portion. The I/O channel is coupled to the SD-bus while system ROM is coupled to the XD-bus. To accommodate the fact that the swapper is internal, the support chip provides independent direction control of the high and low order buffers between the XD-bus and the SD-bus.

Abstract: A technique for providing external mode select information to a chip capable of operating in different modes without adding pin overhead. One of the normal signal pins of the chip is used as an input pin for a brief period of time at power-on before the chip becomes fully operational. During this time, a mode select signal from outside is communicated onto the pin and latched into the chip, where it remains during subsequent normal operation of the chip.

Abstract: An integrated circuit chip that facilitates connecting peripheral devices to an MCA Micro Channel Architecture bus system. With the present invention manufacturers of adapter boards and cards can easily interface peripheral devices to an MCA bus. With the present invention the MCA interface is segmented in a different manner than it is segmented in prior art adapters. In the approach utilized with the present invention the interface has been partitioned so that the microchannel signals and the protocol signals common to all functions are contained on an interface chip.

Abstract: The present invention provides a contrast enhancing method and circuit for mapping color signals into signals for driving a display which is capable of displaying shades of gray. With the present invention a preliminary translation is first made between a foreground-background color combination and the various shades of gray that can be displayed. The contrast or separation between the foreground level of gray and the background level of gray produced by this preliminary translation is then compared to parameters set by the operator.

Abstract: An interactive graphics and audio communications system is disclosed. The system enables users to communicate audibly and graphically over a single telephone connection.