Abstract: A Fermi threshold voltage FET has Germanium implanted to form a shallow abrupt transition between the semiconductor substrate dopant type, or well dopant type, and a counter doping layer of opposite type closely adjacent the surface of the semiconductor substrate. Germanium is a charge neutral impurity in silicon that significantly reduces the diffusion motion of other impurity dopants, such as As, P, In, and B in the regions of silicon where Ge resides in significant quantities (i.e. greater than 1E19 cm sup3).

Abstract: A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer.

Abstract: A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer.

Abstract: Spacers are formed having widths that vary as a function of the spacing between the mandrels upon which the conformal material that defines the spacers is deposited and etched. As the spacing between adjacent mandrels decreases, the width of the resulting spacers decreases. The correlation between mandrel spacing and sidewall structure width is independent of the thickness of the conformal material as-deposited. As the spacing between the mandrels decreases, the decrease in width becomes more pronounced, particularly at mandrel spacings of five microns or less. Thus, by making adjacent mandrels closer together or further apart and adjusting mandrel height, active/passive components having differing widths/lengths may be formed from the same conformal layer.

Abstract: A method for reducing the susceptibility of integrated circuit dynamic memory devices to environmentally produced radiation, such as alpha particles, in which a buried layer, having a majority carrier concentration substantially equal to or greater than the concentration of free carriers generated by the radiation and being between one and four orders of magnitude greater concentration than that of the semiconductor substrate, is ion implanted within a few microns of the substrate surface after at least one major high temperature processing step in the manufacturing process has been completed.

Abstract: A method of providing less than one micron p-n junction regions for IGFET devices in which a high concentration of arsenic is implanted so that its peak lies near the surface of a semiconductor substrate. Phosphorus is also implanted with an energy to provide a maximum concentration below that of the arsenic and of a magnitude at least one order of magnitude less than that of arsenic. An oxidation/anneal step thermally diffuses the implanted ions to form a junction less than one micron in thickness.