Abstract: A decoder for selected linear error correcting codes, such as a BCH code, uses relatively low-speed circuitry to determine syndromes and corresponding error locations for correcting the code. In a specific embodiment of a BCH linear cyclic invariant error correcting code, only cyclic invariants are stored in Read Only Memory such that the storage requirements of the Read Only Memory are minimized, and table look-up techniques are employed to speed apparent computation. In another specific embodiment of a linear error correcting codes, a Read Only Memory is used to store precomputed indicia of possible errors in the code word, and table look-up techniques are employed to determine one or more syndromes. The table look-up method avoids the complexity of error locating polynomials, algebraic root finders and real-time computation while reducing computation time.

Abstract: A method and apparatus for combining encoding and modulation creates signal sets from available amplitude and phase modulations by indexing ordered subspaces. The subspaces need not be limited to the class of subspaces known as binary subspaces. The resultant signal sets, for a preselected power and bandwidth, are widely separated and unlikely to be confused by the effects of channel noise. Such signals can be in either finite block or convolutional form, depending on the natural format of the desired transmission. Further according to the invention are basic apparatus for encoding and modulating as well as demodulating and decoding a signal in accordance with the invention. Specifically, a method is provided for decoding the incorporates a specific type of decoding/demodulation techniques which develops accurate estimates of the information from the received signal in a computationally efficient manner and which permits high speed operation using softdecision decoders.

Abstract: A system and procedure for organizing a digital memory by incorporating error correcting circuitry and error detecting circuitry into the memory based on the graph of an error-correcting code in tree form. The error detecting circuitry detects a variety of multiple errors in stored binary bits, and in addition detects certain failures in the memory circuitry. One embodiment coordinates a series of independent memory subarrays in an interdependent manner so that all of the bits in an arbitrarily large memory are organized so as to form several long code words in a single-error-correcting double-error-detecting code. Another embodiment organizes all of the bits in the memory so that they form a single codeword in a double-error-correcting, triple-error-detecting code derived from a projective plane. Coding efficiency is high: in the cases of a 256K memory, including the required parity check bits, only (33/32) 256K bits, approximately, must be stored.

Abstract: A method and apparatus for constructing long error-correcting codes from one or more shorter error-correcting codes, referred to as subcodes, and a bipartite graph. The graph specifies carefully chosen subsets of the digits of the new codes that must be codewords in one of the shorter subcodes. Lower bounds on the rate and the minimum distance of the new code are derived in terms of the parameters of the graph and the subcodes. Both the encoders and decoders employed take advantage of the code's explicit decomposition into subcodes to decompose and simplify the associated computational processes. Bounds on the performance of two specific decoding algorithms are established, and the asymptotic growth of the complexity of decoding for two types of codes and decoders is analyzed. The decoders are able to make effective use of probabilistic information supplied by the channel receiver, such as reliability information, without greatly increasing the number of computations required.