Abstract: Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.

Abstract: A device for improving a golfer's swing, the device having a training handle for a golf club wherein the golf club has a longitudinal shaft having at its superior end a gripping area and at its inferior end a head, the training handle originating on or immediately inferior to the gripping area and extending perpendicularly from the longitudinal shaft, the handle being oriented such that it is parallel to the longitudinal axis of the golf club head.

Abstract: Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.

Abstract: Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.

Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.

Abstract: A seed placement device (10) that is comprised of a seeding strip (12) and a boring tool (32). The seeding strip (12) has a multiplicity of equidistant holes (26) extending therethrough, and the boring tool (32) has an upper end (34), a shank (36) and a lower end (38) that terminates in a point (40). The seed placement device (10) is designed to quickly and easily allow a person to place a multiplicity of seeds (90) in the ground (92). Once the seeding strip (12) is placed in a desired location on the ground (92), a person inserts the boring tool (32) through each of the holes (26) and into the ground (92), thus creating a series of equidistant cavities (94), into each of which at least one seed (90) can be placed.

Abstract: A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.

Abstract: A method and apparatus for destroying the metallic portion of an elongate medical instrument, such as a hypodermic needle, by locating the instrument in the apparatus in a position where the tip of the instrument electrically engages a contact surface of a first and a second electrode. The electrodes each have an electrical contact surface disposed in opposition and separated by a gap from each other, and each electrode is in electrical contact with a power source. The electric potential between the electrodes is sufficient to induce electrical resistance burning of the tip of the instrument when an electrical current is passed through the tip between the electrodes. During operation of the apparatus, the instrument is progressively advanced longitudinally relative to the electrodes to progressively consumes the shaft of the medical instrument as the burning tip continuously advances from the start position to a finish position.

Abstract: A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.

Abstract: A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.

Abstract: An amplifier of a type having complementary output nodes in a data output mode of operation. When an external output enable signal is at a low level, the amplifier is enabled to output a data signal. When the output enable signal is set into a high level, the amplifier is brought into an output disable mode, in which both of its output nodes are set to a low level. The amplifier contains logic circuitry for supplying the output nodes with the data signal and output enable signal. In the output disable mode, a shunting circuit is arranged between the output nodes to provide two discharge paths for a charge stored at one of the output nodes when the signal at this output node transfers from a high level to a low level.

Abstract: An apparatus for destroying a medical instrument includes a housing having a wall member with an aperture disposed therein. A first electrical connector member is mounted adjacent the wall member of the housing for engaging a portion of a medical instrument inserted through the aperture in the wall member. A second electrical connector member is disposed within the housing for engaging an end portion of a medical instrument inserted through the aperture in the wall member. The first and second electrical connector members are provided to be selectively connected to a supply of electric current for destroying the medical instrument by transmitting current from the first electrical connector member to the second electrical connector member and through a medical instrument for melting the same. The second electrical connector member may be spring biased toward the aperture and pivotally mounted.

Abstract: A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

Abstract: A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

Abstract: A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control inverter having a switching threshold voltage higher than that of the first control inverter. The gate of the N channel transistor in the second inverter is controlled by a third control inverter having a switching threshold voltage lower than that of the first control inverter.

Abstract: A greenhouse having a hollow framework structure (20) with water under pressure fluidly disposed inside characterizing a combined structural frame and water pipe. A number of spray nozzles (34) are attached to the framework at appropriate locations and drippers (60) are, likewise, attached. The nozzles atomize the water increasing the humidity inside the greenhouse and the drippers water the plants beneath. A transparent enclosure consisting of walls (42) and a roof (44) envelope the framework and are attached with straps (50). Air ciculation is achieved by windows (52) and vents (54) along with an optional fan (56).

Abstract: A non-return valve, comprising a perforate, hollow, conoidally-shaped valve seat defining a cavity of circular cross-section, a hollow, conoidally-shaped diaphragm of elastomerically deformable material and means for securing the diaphragm within the valve seat, so that the entire outer periphery of the rim of the diaphragm is in sealing engagement with the inner periphery of the rim of the valve seat, the diaphragm having an undeformed shape, prior to insertion of the valve member into the valve seat, such that the cross-section of the diaphragm, at least throughout a part of its axial length excluding the rim, is non-annular and bounded by non-circular inner and outer peripheries.