Patents by Inventor Robert Maddox

Robert Maddox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240012772
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 11, 2024
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 11741030
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20220114122
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 11269793
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20210117350
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: December 25, 2020
    Publication date: April 22, 2021
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 10875248
    Abstract: The present invention relates generally to methods of fabricating surface topography based on a scanned surface topography. The method converts 3D scanned surface topography data that have submicron resolution to digital formats that can be stored, manipulated, or tiled, and used as an input for replicating the surface topography with submicron resolution on another substrate. The digitized surface topography data is then converted to input for 1) 3D printing to replicate the scanned surface topography with submicron resolution, with or without a subsequent coating layer or layers to impart additional properties and/or features, 2) 3D printing a master that replicates the scanned surface topography with submicron resolution, which will be used for fast replica molding of the surface topography onto another substrate, and 3) creating a photomask with submicron resolution for transferring the surface topography to a metal substrate surface through subsequent photolithography and etching processes.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 29, 2020
    Assignee: Board Of Trustees Of The University Of Arkansas
    Inventors: Mahyar Afshar Mohajer, Josue Goss, Dipankar Choudhury, Min Zou, Shelby Robert Maddox
  • Publication number: 20200356502
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20190391939
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.
    Type: Application
    Filed: February 25, 2019
    Publication date: December 26, 2019
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20190248073
    Abstract: The present invention relates generally to methods of fabricating surface topography based on a scanned surface topography. The method converts 3D scanned surface topography data that have submicron resolution to digital formats that can be stored, manipulated, or tiled, and used as an input for replicating the surface topography with submicron resolution on another substrate. The digitized surface topography data is then converted to input for 1) 3D printing to replicate the scanned surface topography with submicron resolution, with or without a subsequent coating layer or layers to impart additional properties and/or features, 2) 3D printing a master that replicates the scanned surface topography with submicron resolution, which will be used for fast replica molding of the surface topography onto another substrate, and 3) creating a photomask with submicron resolution for transferring the surface topography to a metal substrate surface through subsequent photolithography and etching processes.
    Type: Application
    Filed: February 11, 2019
    Publication date: August 15, 2019
    Applicant: BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
    Inventors: Mahyar Afshar Mohajer, Josue Goss, Dipankar Choudhury, Min Zou, Shelby Robert Maddox
  • Patent number: 10268583
    Abstract: A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Robert Beers, Robert G. Blankenship, Robert J. Safranek, Jeff Willey, Robert A. Maddox, Aaron T. Spink
  • Patent number: 10248591
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 9767125
    Abstract: Configurations and applications for data signatures are disclosed. Such a data signature may be specific to a particular data element in a data set, and may define this particular data element in relation to one or more other data elements. These data signatures may be used for any appropriate purpose. For instance, data signatures of this type may be generated from a given data set and may be used to analyze this data set in at least some respect, including to identify one or more features in the data set (e.g., for feature extraction purposes). Data signatures of this type may also be used in at least some fashion to generate a presentation or output that relates to the associated data set (including digitally on an appropriate display, as well as in “hard copy” form).
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: September 19, 2017
    Assignee: H-D Asset Management LLC
    Inventors: Robert Maddox Brinson, Jr., Nicholas Levi Middleton, Robert Wayne White
  • Publication number: 20170109315
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 9626321
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20150089161
    Abstract: A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 26, 2015
    Inventors: Robert Beers, Robert G. Blankenship, Robert J. Safranek, Jeff Willey, Robert A. Maddox, Aaron T. Spink
  • Publication number: 20140112339
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 24, 2014
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul C. Shah, Sitaraman V. Iyer, Bill Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20140115268
    Abstract: A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined.
    Type: Application
    Filed: March 15, 2013
    Publication date: April 24, 2014
    Inventors: Robert Beers, Robert G. Blankenship, Robert J. Safranek, Jeff Willey, Robert A. Maddox, Aaron T. Spink
  • Patent number: 8671071
    Abstract: Configurations and applications for data signatures are disclosed. Such a data signature may be specific to a particular data element in a data set, and may define this particular data element in relation to one or more other data elements. These data signatures may be used for any appropriate purpose. For instance, data signatures of this type may be generated from a given data set and may be used to analyze this data set in at least some respect, including to identify one or more features in the data set (e.g., for feature extraction purposes). Data signatures of this type may also be used in at least some fashion to generate a presentation or output that relates to the associated data set (including digitally on an appropriate display, as well as in “hard copy” form).
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: March 11, 2014
    Assignee: Apokalyyis, Inc.
    Inventors: Robert Maddox Brinson, Jr., Nicholas Levi Middleton, Robert Wayne White
  • Patent number: 8608319
    Abstract: A multi-layer projection display including first and second panels separated by a predetermined distance, wherein at least a portion of the first panel overlaps at least a portion of the second panel, and the first panel is disposed between a viewing location and the second panel. The display also includes a controller configured to cause the first and second panels to alternate between substantially opaque and substantially transparent states at a determined frequency, such that the first panel is substantially opaque when the second panel is substantially transparent, and the second panel is substantially opaque when the first panel is substantially transparent. The display further includes a projector configured to project an image onto the first panel when the first panel is substantially opaque, and further configured to project the image onto the second panel when the second panel is substantially opaque.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: December 17, 2013
    Assignee: IGT
    Inventors: Chauncey W. Griswold, Robert Maddox
  • Publication number: 20130030919
    Abstract: Technologies for targeting listings based on user-supplied profile and interest data are presented herein. In one aspect, user-supplied profile and interest data is received from a user. Targeted business listings are generated for the user based on the user-supplied profile and interest data. The targeted business listings are then provided to the user.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 31, 2013
    Inventors: Robert Maddox Brinson, JR., Madison Elizabeth Brinson, Tina Brinson Cox, Rebecca Frierson Maddox, Hal Hunt Blakeslee