Abstract: A pipelined computer system with power management control in accordance with one or both of a power management signal and a power management instruction.

Abstract: A method and apparatus is described that allow the creation of virtual routing domains in an IP network. These virtual routing domains allow individual networks to be configures so that it appears that its routing domain covers the entire IP address space. A network processing system is used to implement the virtual routing domains and to allow network traffic to cross the individual routing domains. The network processing system is able to use application layer information to allow the crossing of virtual routing domain boundaries. By examining application layer information the network processing system is able to look up customer/user information and use that information to determine destination virtual routing domains and route otherwise unroutable addresses between domains.

Abstract: An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.

Abstract: A method of reducing noise in an audio signal, comprising the steps of: using a furrow filter to select spectral components that are narrow in frequency but relatively broad in time; using a bar filter to select spectral components that are broad in frequency but relatively narrow in time; analyzing the relative energy distribution between the output of the furrow and bar filters to determine the optimal proportion of spectral components for the output signal; and reconstructing the audio signal to generate the output signal. A second pair of time-frequency filters may be used to further improve intelligibility of the output signal. The temporal relationship between the furrow filter output and the bar filter output may be monitored so that the fricative components are allowed primarily at boundaries between intervals with no voiced signal present and intervals with voice components. A noise reduction system for an audio signal.

Abstract: A signal-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to at least one control signal.

Abstract: An apparatus and method for traversing a network address translation/firewall device to maintain a registration between first and second devices separated by the firewall device are provided. In one example, the method includes intercepting a registration message from the first device to the second device. A determination is made based on a first timeout period defined by the second device as to whether it is time to renew the first device's registration. If it is time to renew the first device's registration, the registration message is forwarded to the second device. A response message that includes the first timeout period is intercepted, and the first timeout period is replaced with a second timeout period based on a binding lifetime of the firewall device before forwarding the response message to the first device.

Abstract: A signal-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to at least one control signal.

Abstract: A method and system are described for resolving problems created by implementing multiple networks using private IP addresses and layer two tunneling protocols is described. A network processing system is operable to map flows from private IP addresses and ports on layer two tunneling protocol networks to public IP addresses and ports using the private IP addresses and ports and identifiers for the layer two tunneling protocol network. The network processing system uses its own public IP addresses and ports to anchor the traffic from the private network and performs the required mapping to pass traffic between the public and private networks.

Abstract: A pipelined data processor with instruction-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry and circuitry for generating and controlling at least one clock signal are responsive to an instruction executed by the pipeline subcircuitry by selectively disabling a clock signal to the pipeline subcircuitry.

Abstract: A pipelined data processor with signal-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry, and circuitry for generating and controlling at least one clock signal are responsive to at least one control signal by disabling a clock signal to the pipeline subcircuitry.

Abstract: A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal.

Abstract: A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal.

Abstract: A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal.

Abstract: A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal.

Abstract: A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal.

Abstract: A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal.

Abstract: In accordance with the presently claimed invention, power consumption reduction control is provided to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.

Abstract: Power consumption reduction control circuitry external and coupled to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.

Abstract: A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode.

Abstract: A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode.