Abstract: A method of modeling a combinatorial gate which includes providing a data signal input at the combinatorial gate, providing a clock signal input at the combinatorial gate, propagating the clock signal as an output signal when the output of the combinatorial gate corresponds to the clock signal, and propagating the data signal as an output when the output of the combinatorial gate corresponds to the data signal, the propagating the data signal modeling a near domino function.

Abstract: A method of using static timing analysis to extract implicit connectivity graph information. The method includes creating a unique clock waveform, defining a clock domain for the clock waveform, injecting the clock domain into a control node, propagating timing events from the control node to a transitively adjacent observation node, and retrieving transitively adjacent control node information to determine path delay information from the control node to the transitively adjacent observation node based upon propagation of timing events.