Abstract: Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU.

Abstract: Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time.

Abstract: A new distributed control mechanism for managing bi-directional interfaces of symmetrical multiprocessor systems in such a manner as to minimize the latency to storage, yet fairly distribute the use of the interfaces amongst the various components. This bi-directional interface can be designed to perform with differing characteristics depending upon the direction of information flow. These characteristics are implemented into the control logic of the source and destination components interconnected by the bi-directional interface, thus yielding two interface behaviors using only one interface. Each component is able to track the state of the interface by using only its own request state in conjunction with the detected request state of the opposing component, when both units are operating under the joint control algorithm present in the control logic of the source and destination component.