Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

Abstract: A method of connecting signal lines between an integrated circuit (IC) die and a carrier or external circuit, and corresponding apparatus. Techniques for adjusting magnetic coupling between terminated signal lines include splitting a return path for termination current and disposing one nearby on either side of the terminated signal line, creating two small termination current loops conducting in opposite directions; using separate terminating impedances, which may be unequal, to control current in each of the loops; and arranging major axes of the termination current loops for a signal to be perpendicular to those of the isolation-target signal. Capacitive coupling adjustments include routing ground potential termination current return connections nearby the signal connection to shield it from the isolated signal line, using dual overlapping connections to shield each return path, and adjusting dielectric material proximity to the signal paths.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: A method of connecting signal lines between an integrated circuit (IC) die and a carrier or external circuit, and corresponding apparatus. Techniques for adjusting magnetic coupling between terminated signal lines include splitting a return path for termination current and disposing one nearby on either side of the terminated signal line, creating two small termination current loops conducting in opposite directions; using separate terminating impedances, which may be unequal, to control current in each of the loops; and arranging major axes of the termination current loops for a signal to be perpendicular to those of the isolation-target signal. Capacitive coupling adjustments include routing ground potential termination current return connections nearby the signal connection to shield it from the isolated signal line, using dual overlapping connections to shield each return path, and adjusting dielectric material proximity to the signal paths.