Patents by Inventor Robert Mason Hanrahan
Robert Mason Hanrahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085479Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventor: Robert Mason HANRAHAN
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Patent number: 11867761Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.Type: GrantFiled: August 20, 2021Date of Patent: January 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Robert Mason Hanrahan
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Patent number: 11853664Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.Type: GrantFiled: September 28, 2021Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
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Patent number: 11239694Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.Type: GrantFiled: October 30, 2019Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Deric Wayne Waters, Robert Mason Hanrahan
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Publication number: 20220012391Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.Type: ApplicationFiled: September 28, 2021Publication date: January 13, 2022Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
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Publication number: 20210382112Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.Type: ApplicationFiled: August 20, 2021Publication date: December 9, 2021Inventor: Robert Mason HANRAHAN
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Patent number: 11163926Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.Type: GrantFiled: August 18, 2020Date of Patent: November 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
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Patent number: 11125820Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.Type: GrantFiled: November 13, 2018Date of Patent: September 21, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Robert Mason Hanrahan
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Publication number: 20200380187Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
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Patent number: 10789399Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.Type: GrantFiled: August 14, 2019Date of Patent: September 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
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Publication number: 20200067346Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.Type: ApplicationFiled: October 30, 2019Publication date: February 27, 2020Inventors: Deric Wayne Waters, Robert Mason Hanrahan
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Publication number: 20190370428Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.Type: ApplicationFiled: August 14, 2019Publication date: December 5, 2019Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
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Patent number: 10498167Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.Type: GrantFiled: June 8, 2017Date of Patent: December 3, 2019Assignee: Texas Instruments IncorporatedInventors: Deric Wayne Waters, Robert Mason Hanrahan
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Publication number: 20190331734Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.Type: ApplicationFiled: November 13, 2018Publication date: October 31, 2019Inventor: Robert Mason HANRAHAN
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Patent number: 10423746Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.Type: GrantFiled: July 22, 2016Date of Patent: September 24, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
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Publication number: 20170358947Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.Type: ApplicationFiled: June 8, 2017Publication date: December 14, 2017Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Deric Wayne Waters, Robert Mason Hanrahan
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Publication number: 20170024505Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.Type: ApplicationFiled: July 22, 2016Publication date: January 26, 2017Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
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Patent number: 7343140Abstract: A tuner is provided for selecting, independently of each other, a plurality of radio frequency channels for simultaneous reception. The tuner comprises a plurality of up converters whose outputs are combined in a combiner. Each up converter operates independently of the other up converters to select a channel from a multi channel input signal and to convert the selected channel to a first high intermediate frequency. The intermediate frequencies of the up converters are different from each other. The common signal from the combiner is supplied to a down converter which converts the signals at different high intermediate frequencies to signals at different lower intermediate frequencies. Thus, the signals from the combiner and from the down converter carry all of the selected channels at different intermediate frequencies. The signal from the down converter is subsequently processed to separate the selected channels and demodulate them.Type: GrantFiled: April 10, 2003Date of Patent: March 11, 2008Assignee: Intel CorporationInventor: Robert Mason Hanrahan
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Publication number: 20040204034Abstract: A tuner is provided for selecting, independently of each other, a plurality of radio frequency channels for simultaneous reception. The tuner comprises a plurality of up converters whose outputs are combined in a combiner. Each up converter operates independently of the other up converters to select a channel from a multi channel input signal and to convert the selected channel to a first high intermediate frequency. The intermediate frequencies of the up converters are different from each other. The common signal from the combiner is supplied to a down converter which converts the signals at different high intermediate frequencies to signals at different lower intermediate frequencies. Thus, the signals from the combiner and from the down converter carry all of the selected channels at different intermediate frequencies. The signal from the down converter is subsequently processed to separate the selected channels and demodulate them.Type: ApplicationFiled: April 10, 2003Publication date: October 14, 2004Inventor: Robert Mason Hanrahan