Patents by Inventor Robert Mason Hanrahan

Robert Mason Hanrahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085479
    Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventor: Robert Mason HANRAHAN
  • Patent number: 11867761
    Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: January 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Robert Mason Hanrahan
  • Patent number: 11853664
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: December 26, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Patent number: 11239694
    Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deric Wayne Waters, Robert Mason Hanrahan
  • Publication number: 20220012391
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 13, 2022
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Publication number: 20210382112
    Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.
    Type: Application
    Filed: August 20, 2021
    Publication date: December 9, 2021
    Inventor: Robert Mason HANRAHAN
  • Patent number: 11163926
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: November 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Patent number: 11125820
    Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: September 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Robert Mason Hanrahan
  • Publication number: 20200380187
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Patent number: 10789399
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: September 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Publication number: 20200067346
    Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Deric Wayne Waters, Robert Mason Hanrahan
  • Publication number: 20190370428
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Patent number: 10498167
    Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: December 3, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Deric Wayne Waters, Robert Mason Hanrahan
  • Publication number: 20190331734
    Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.
    Type: Application
    Filed: November 13, 2018
    Publication date: October 31, 2019
    Inventor: Robert Mason HANRAHAN
  • Patent number: 10423746
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: September 24, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Publication number: 20170358947
    Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 14, 2017
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deric Wayne Waters, Robert Mason Hanrahan
  • Publication number: 20170024505
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 26, 2017
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Patent number: 7343140
    Abstract: A tuner is provided for selecting, independently of each other, a plurality of radio frequency channels for simultaneous reception. The tuner comprises a plurality of up converters whose outputs are combined in a combiner. Each up converter operates independently of the other up converters to select a channel from a multi channel input signal and to convert the selected channel to a first high intermediate frequency. The intermediate frequencies of the up converters are different from each other. The common signal from the combiner is supplied to a down converter which converts the signals at different high intermediate frequencies to signals at different lower intermediate frequencies. Thus, the signals from the combiner and from the down converter carry all of the selected channels at different intermediate frequencies. The signal from the down converter is subsequently processed to separate the selected channels and demodulate them.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventor: Robert Mason Hanrahan
  • Publication number: 20040204034
    Abstract: A tuner is provided for selecting, independently of each other, a plurality of radio frequency channels for simultaneous reception. The tuner comprises a plurality of up converters whose outputs are combined in a combiner. Each up converter operates independently of the other up converters to select a channel from a multi channel input signal and to convert the selected channel to a first high intermediate frequency. The intermediate frequencies of the up converters are different from each other. The common signal from the combiner is supplied to a down converter which converts the signals at different high intermediate frequencies to signals at different lower intermediate frequencies. Thus, the signals from the combiner and from the down converter carry all of the selected channels at different intermediate frequencies. The signal from the down converter is subsequently processed to separate the selected channels and demodulate them.
    Type: Application
    Filed: April 10, 2003
    Publication date: October 14, 2004
    Inventor: Robert Mason Hanrahan