Patents by Inventor Robert Mateescu

Robert Mateescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250238202
    Abstract: Multiply and accumulate (MAC) operations typically involve extremely large amounts of data and large numbers of operations. As such, they are extremely computationally intensive, involving large numbers of data transfers and consuming large amounts of time and power. To address these problems, the following presents methods of realizing a MAC engine in a 3D NAND flash die. The engine takes as input two vectors and outputs their dot product. The dot product of two vectors is the building block of matrix multiplication. The 3D NAND MAC engine presented here can be used to implement modern machine learning algorithms, in particular Neural Networks. The two vector operands are not programed into the NAND memory cells, therefore the endurance of the device is not compromised.
    Type: Application
    Filed: January 19, 2024
    Publication date: July 24, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Robert Mateescu, Cyril Guyot, Richard New
  • Patent number: 12362029
    Abstract: A storage device processes storage-free stuck bits information when writing and reading stored on the memory device. A controller encodes the data with cyclic error-correcting codes to generate a codeword and determines that a location in the memory device where codeword is be stored includes a stuck bit. Rather than storing the stuck bits information, when storing the codeword, the controller generates an encoding mask, adds the encoding mask to the codeword to generate encoded data, and stores the encoded data on the memory device. When reading the encoded data, the controller generates a list of decoding masks including the encoding mask, goes through the lists and adds a decoding mask to the encoded data. The controller decodes the encoded data with the encoding mask from the list and returns the data.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: July 15, 2025
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert Mateescu, Cyril Guyot, Ivana Djurdjevic
  • Publication number: 20250190302
    Abstract: A storage device minimizes redundancy for stuck bit codes when writing a message to a memory device. A controller generates a set of masks that are codewords and that include values that correspond to stuck bit values. The set of masks may include full length codewords or shortened codewords. When the controller receives a message including a predefined number of label bits and determines that a location in the memory device where the message is be stored includes two stuck bits, the controller encodes the message to produce a first message codeword. The controller then locates a mask from the set of masks, wherein when the mask is added to the first message codeword, any two stuck message bits are masked. The controller computes a final message codeword using the first message codeword and the mask and stores the final message codeword on the memory device.
    Type: Application
    Filed: December 8, 2023
    Publication date: June 12, 2025
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: IVANA DJURDJEVIC, CYRIL GUYOT, ROBERT MATEESCU
  • Publication number: 20250157562
    Abstract: A storage device processes storage-free stuck bits information when writing and reading stored on the memory device. A controller encodes the data with cyclic error-correcting codes to generate a codeword and determines that a location in the memory device where codeword is be stored includes a stuck bit. Rather than storing the stuck bits information, when storing the codeword, the controller generates an encoding mask, adds the encoding mask to the codeword to generate encoded data, and stores the encoded data on the memory device. When reading the encoded data, the controller generates a list of decoding masks including the encoding mask, goes through the lists and adds a decoding mask to the encoded data. The controller decodes the encoded data with the encoding mask from the list and returns the data.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 15, 2025
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: ROBERT MATEESCU, CYRIL GUYOT, IVANA DJURDJEVIC
  • Publication number: 20240146700
    Abstract: A client device encodes at least two datasets using one or more encoding functions to generate encoded data portions that are encrypted using a first key according to an approximate Fully Homomorphic Encryption (FHE) scheme to generate encrypted data portions that are sent to a plurality of servers. Encrypted results are received from at least a subset of servers of the plurality of servers. Each encrypted result is calculated by a respective server using at least two encrypted data portions received by the server. The encrypted results are decrypted using a secret key according to the approximate FHE scheme to derive decrypted encoded results that are decoded using an approximate decoding function. In one aspect, an encrypted result is calculated by each server by evaluating a multivariate function using the at least two encrypted data portions received by the server.
    Type: Application
    Filed: August 8, 2023
    Publication date: May 2, 2024
    Inventors: Dongwoo Kim, Mahdi Soleymani, Robert Mateescu, Cyril Guyot
  • Patent number: 11487580
    Abstract: A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yongjune Kim, Yuval Cassuto, Robert Mateescu, Cyril Guyot
  • Publication number: 20210073036
    Abstract: A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yongjune Kim, Yuval Cassuto, Robert Mateescu, Cyril Guyot
  • Patent number: 10228878
    Abstract: Technology is described for performing wear leveling in non-volatile storage. Mapping from logical addresses to intermediate addresses may be performed without the use of a mapping table having an entry for each page. Intermediate addresses may be mapped to physical addresses in a physical address space partitioned into a number of buckets. Wear-leveling may be performed within each bucket by, for example, rotating data within a bucket. The bucket size and rotation rate may be selected to keep wear on the memory cells well with tolerance. The mapping from logical addresses to intermediate addresses may periodically be changed, with an associated move of data from one bucket to another bucket to provide additional wear leveling.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 12, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert Mateescu, Cyril Guyot
  • Patent number: 10223018
    Abstract: The amount of remapping data in a file system of a memory device is reduced. In one aspect, for each request access, e.g., read or write operation, the memory cells of a primary physical address are evaluated. If the evaluation indicates the memory cells are good, the read or write operation proceeds. If the memory cells have a failure such as uncorrectable errors, the primary physical address is hashed to obtain an auxiliary physical address. If the auxiliary physical address is not available, the primary physical address can be hashed again to obtain another auxiliary physical address. In another aspect, per-page remapping is performed until a threshold number of bad pages in a block are detected, after which the entire block is remapped. In another aspect, pages of a block are remapped to auxiliary pages based on a block identifier.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 5, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Kiran Gunnam, Robert Mateescu
  • Patent number: 10164655
    Abstract: Techniques for generating parities and repairing data erasures using a cache oblivious encoding algorithm are disclosed. The system includes an encoding module which receives a request to recreate data for a subset of a plurality of content stores from a storage manager. The encoding module generates a new first parity and a new second parity using the remaining content in the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second parity for the plurality of content stores. The encoding module may recreate the data for the plurality of content stores using the first portion of the requested data and the second portion of the requested data.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 25, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cyril Guyot, Robert Mateescu, Lluis Pamies-Juarez, Filip Blagojevic
  • Patent number: 10120576
    Abstract: Small objects are efficiently stored with erasure codes by combining a small object with other small objects and/or large objects to form a single large object for chunking, and providing early notification of permanent storage to the sources of the objects to prevent small objects from becoming stale while waiting for additional objects to be combined.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: November 6, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Adam Manzanares, Lluis Pamies-Juarez, Cyril Guyot, Koen De Keyser, Mark Christiaens, Robert Mateescu
  • Publication number: 20180307431
    Abstract: The amount of remapping data in a file system of a memory device is reduced. In one aspect, for each request access, e.g., read or write operation, the memory cells of a primary physical address are evaluated. If the evaluation indicates the memory cells are good, the read or write operation proceeds. If the memory cells have a failure such as uncorrectable errors, the primary physical address is hashed to obtain an auxiliary physical address. If the auxiliary physical address is not available, the primary physical address can be hashed again to obtain another auxiliary physical address. In another aspect, per-page remapping is performed until a threshold number of bad pages in a block are detected, after which the entire block is remapped. In another aspect, pages of a block are remapped to auxiliary pages based on a block identifier.
    Type: Application
    Filed: April 19, 2017
    Publication date: October 25, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Kiran Gunnam, Robert Mateescu
  • Patent number: 9959166
    Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 1, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Robert Mateescu, Zvonimir Z. Bandic, Yongjune Kim, Seung-Hwan Song
  • Publication number: 20180034475
    Abstract: Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which receives a request to recreate data for a subset of a plurality of content stores. The encoding module generates a new first parity and a new second parity using a subset of remaining content from the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first subset of an original first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second subset of an original second parity for the plurality of content stores. The encoding module may recreate the data for the content store using the first portion of the requested data and the second portion of requested data.
    Type: Application
    Filed: October 5, 2017
    Publication date: February 1, 2018
    Inventors: Robert Mateescu, Lluis Pamies-Juarez, Cyril Guyot
  • Patent number: 9830219
    Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 28, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Robert Mateescu, Yongjune Kim, Zvonimir Z. Bandic, Seung-Hwan Song
  • Patent number: 9793922
    Abstract: Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which receives a request to recreate data for a subset of a plurality of content stores. The encoding module generates a new first parity and a new second parity using a subset of remaining content from the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first subset of an original first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second subset of an original second parity for the plurality of content stores. The encoding module may recreate the data for the content store using the first portion of the requested data and the second portion of requested data.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 17, 2017
    Assignee: HGST Netherlands B.V.
    Inventors: Robert Mateescu, Lluis Pamies-Juarez, Cyril Guyot
  • Patent number: 9778859
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 3, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dejan Vucinic, Zvonimir Z. Bandic, Cyril Guyot, Robert Mateescu, Qingbo Wang
  • Publication number: 20170262187
    Abstract: Small objects are efficiently stored with erasure codes by combining a small object with other small objects and/or large objects to form a single large object for chunking, and providing early notification of permanent storage to the sources of the objects to prevent small objects from becoming stale while waiting for additional objects to be combined.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 14, 2017
    Inventors: Adam MANZANARES, Lluis PAMIES-JUAREZ, Cyril GUYOT, Koen De KEYSER, Mark CHRISTIAENS, Robert MATEESCU
  • Patent number: 9704594
    Abstract: The present disclosure relates to apparatus, systems, and methods that address the migration of least significant in memory cells due to inter-cell interference (ICI). The disclosed embodiments include a control unit that is configured to characterize the vulnerability of memory cells to ICI, and appropriately encode data stored in the vulnerable memory cells to address ICI. This encoding scheme, referred to as “stuck-at” encoding scheme, can be separate from the generic error correcting code encoding. The stuck-at encoding scheme can decrease the bit error rate of flash memory devices.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: July 11, 2017
    Assignee: Western Digital Technolgies, Inc.
    Inventors: Minghai Qin, Robert Mateescu, Seung-Hwan Song, Zvonimir Z. Bandic
  • Publication number: 20170192846
    Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventors: Robert MATEESCU, Zvonimir Z. BANDIC, Yongjune KIM, Seung-Hwan SONG