Abstract: The present disclosure relates to methods of forming interconnects to bond package assemblies together. In one embodiment, copper interconnects are used to bond a package assembly having an organic substrate core to other package assemblies or electronic devices having substrate cores which may include organic cores or inorganic cores, such as silicon, glass, or silicon carbide. In another embodiment, copper interconnects are used to bond a package assembly having an organic substrate core to other package assemblies having organic substrate cores. In another embodiment, a semiconductor package assembly comprising copper or copper alloy interconnects, as herein described.

Abstract: Embodiments of the disclosure describe a method that includes disposing an electrical insulator material over a layer of a ceramic-based material having vias and solid portions between the vias. The vias are filled with an electrically conductive metal that forms electrical paths through the layer of the ceramic-based material. A composite structure is formed that includes portions of the electrical insulator material that are fixed to the solid portions of the layer of the ceramic-based material. The composite structure further includes regions positioned between the portions of the electrical insulator material. The electrical insulator material has a first coefficient of thermal expansion (CTE), the electrically conductive metal has a second CTE, and the ceramic-based material has a third CTE that is greater than the first CTE and less than the second CTE.

Abstract: Integrated circuit (IC) devices having glass layers in package substrates. An IC device substrate may include a solid glass layer and a polymer layer that forms a frame on sidewalls and an upper surface of the glass layer, and the glass layer may include a tab or nubbin that extends through the frame of the polymer layer. The substrate may include electrical vias through the substrate and electrical traces on one or both sides of the substrate. Portions of a glass panel (for example, along saw streets) may be removed and replaced with polymer frame materials. The glass panel may be sawn into glass substrates by sawing through the polymer and through glass bridge portions, which may be of minimal thickness.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: A current and voltage measuring bushing is disclosed. The current and voltage measuring bushing may have a current sensor and a resistive voltage divider commonly located in the bushing. In one or more embodiments, the current and voltage metering bushing may have current and voltage measuring accuracy of 0.3% or better.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

Abstract: A method for determining the thickness of a plurality of coating layers. The method comprises the steps of performing a calibration analysis on calibration data to determine initial values and search limits of optical parameters of the plurality of coating layers, irradiating the plurality of layers with a pulse of THz radiation in the range from 0.01 THz to 10 THz, detecting the reflected radiation to produce a sample response derived from the reflected radiation, producing a synthesized waveform using the optical parameters and predetermined initial thicknesses of the layers, varying the thicknesses and the optical parameters within the search limits to minimize the error measured between the sample response and the synthesized waveform, and outputting the thicknesses of the layers.

Abstract: Disclosed is a system and method to perform payments from a customer to a payee. The system includes a computer-implemented payment server system including a payment scheduling system including a web-based interface to receive payment data, an intelligent routing module to schedule a payment based on the payment data, and a payment staging engine to perform the scheduled payment. The payment server system is to receive, by the web-based interface, payment data for one or more payments. The payment server system is further to determine payment scheduling data for each of the one or more payments. The payment scheduling data includes a determination whether the payment can be made by a requested payment date and a preferred payment network. The payment server system is to transmit payment for each actionable payment via a preferred payment network for each actionable payment.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

Abstract: An apparatus includes a substrate core, which has a first height between a first surface and a second surface opposite the first surface. A die is within the substrate core. The die may include a deep trench capacitor. The die has a second height between a first side of the die and a second side opposite the first side. The first height is greater than the second height. A plurality of conductive vias extend from a plurality of conductive contacts at the first side of the die to the first surface of the substrate core. A material comprising a dielectric is disposed over the die and encapsulates the plurality of conductive vias. In some embodiments, a bond film is in contact with the second side of the die.

Abstract: An apparatus comprises a substrate core comprising a hole extending from an opening at a first surface of the substrate core to a second surface opposite the first surface. A metal layer is over the first surface. The metal layer comprises a plurality of first metal features over a first portion of the opening. The metal layer also includes a second metal feature extending from a sidewall of the hole and over a second portion of the opening. A die is within the hole and coupled to the first metal features by solder features. The die may comprise a capacitor.

Abstract: Apparatuses, capacitor modules, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor module is formed by fabricating capacitor structures along a surface of one or more substrates, cutting the capacitor structures from the one or more substrates and stacking the resultant capacitor structures and substrates into a capacitor module. The capacitor module is then vertically embedded in a package substrate or core.

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

Abstract: A method for determining the thickness of a plurality of coating layers. The method comprises the steps of performing a calibration analysis on calibration data to determine initial values and search limits of optical parameters of the plurality of coating layers, irradiating the plurality of layers with a pulse of THz radiation in the range from 0.01 THz to 10 THz, detecting the reflected radiation to produce a sample response derived from the reflected radiation, producing a synthesized waveform using the optical parameters and predetermined initial thicknesses of the layers, varying the thicknesses and the optical parameters within the search limits to minimize the error measured between the sample response and the synthesized waveform, and outputting the thicknesses of the layers.

Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.

Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.

Abstract: An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and the magnetic material is to rotate a polarization vector of light incoming to the optical interconnect. An optical fiber interface port is immediately adjacent to the first lens. The second lens is immediately adjacent to an optical interface of the optical die.