Patents by Inventor Robert May

Robert May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190370615
    Abstract: State machine methods and apparatus improve computer network functionality relating to natural language communication. In one example, a state machine implements an instance of a workflow to facilitate natural language communication with an entity, and comprises one or more transitions, wherein each transition is triggered by an event and advances the state machine to an outcome state. One or more state machine transitions comprise a work unit that executes one or more computer-related actions relating to natural language communication. An artificial intelligence (AI) agent implements one or more machine learning techniques to monitor inputs/outputs of a given work unit and the respective outcome states of the state machine to determine a status or behavior of the state machine. The AI agent also may generate one or more events to trigger one or more transitions/work units of the state machine, based on one or more inputs monitored by the AI agent and one or more of the machine learning techniques.
    Type: Application
    Filed: April 30, 2019
    Publication date: December 5, 2019
    Inventors: William MURPHY, Matt MCMILLAN, Jon KLEIN, Robert MAY, Byron GALBRAITH
  • Patent number: 10494700
    Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Robert A. May, Sri Ranga Sai Boyapati, Amruthavalli P. Alur, Daniel N. Sobieski
  • Publication number: 20190363059
    Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.
    Type: Application
    Filed: August 8, 2019
    Publication date: November 28, 2019
    Inventors: Hiroki TANAKA, Aleksandar ALEKSOV, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA
  • Publication number: 20190355647
    Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventors: Aleksandar ALEKSOV, Hiroki TANAKA, Robert A. MAY, Kristof DARMAWIKARTA, Changhua LIU, Chung Kwang TAN, Srinivas PIETAMBARAM, Sri Ranga Sai BOYAPATI
  • Patent number: 10453812
    Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Hiroki Tanaka, Aleksandar Aleksov, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta
  • Patent number: 10448244
    Abstract: Systems and methods for facilitating automated configuration and deployment of APs are provided. According to one embodiment, prior to deployment of a wireless access point (AP) within a private network, a cloud service receives a unique identifier associated with the AP and information regarding a network controller within the private network by which the AP will be managed. A mapping is stored by the cloud service between the unique identifier and the information regarding the network controller. Responsive to deployment within the private network, automated configuration processing is performing by the AP, including: (i) establishing a connection with the cloud service; (ii) querying the cloud service for the information regarding the network controller; (iii) configuring itself with the information regarding the network controller; and (iv) establishing a connection to the network controller.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: October 15, 2019
    Assignee: Fortinet, inc.
    Inventor: Robert A. May
  • Publication number: 20190304912
    Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Applicant: INTEL CORPORATION
    Inventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May
  • Publication number: 20190295951
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
  • Publication number: 20190297055
    Abstract: Systems and methods for automated learning of externally defined network assets by a network security device are provided. According to one embodiment, updated information for a network asset associated with a private network is received by a network security device from an external asset management device associated with the private network. The updated information includes a change in a definition or an attribute of the network asset. The existence of a current definition and attribute information for the network asset is determined by the network security device. The current definition and attribute information is dynamically updated based on the updated information by the network security system within a run-time representation of security policy rules within a kernel of a network security operating system without disrupting on-going application of one or more security policy rules defined for the network asset to network traffic directed to or originated by the network asset.
    Type: Application
    Filed: March 26, 2018
    Publication date: September 26, 2019
    Applicant: Fortinet, Inc.
    Inventors: Robert A. May, Mathieu Nantel
  • Patent number: 10406275
    Abstract: An ophthalmic irrigator-aspirator has a handpiece with aspiration and irrigation openings through its distal end. A tip component connects to the handpiece and has an aspiration cannula. A flexible sleeve has an annular hub for watertight connection to the handpiece or a base portion of the tip. The sleeve has an intermediate portion that forms a channel for an irrigation fluid along the exterior of the cannula to an irrigation port in the sleeve. The distal end portion of the sleeve is sized for a watertight connection over the distal portion of the cannula. Such distal end portion of the sleeve has an aspiration port in communication with the cannula aspiration port. The sleeve proximate, intermediate, and distal portions are integral with each other and are formed of a resilient material that allows the sleeve to be tightly fitted on the handpiece or tip base portion and the cannula.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: September 10, 2019
    Assignee: MicroSurgical Technology, Inc.
    Inventors: Kenneth J. Wiljanen, Robert May, Lawrence Laks
  • Patent number: 10403564
    Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Hiroki Tanaka, Robert A. May, Kristof Darmawikarta, Changhua Liu, Chung Kwang Tan, Srinivas Pietambaram, Sri Ranga Sai Boyapati
  • Publication number: 20190206823
    Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: INTEL CORPORATION
    Inventors: Kristof Darmawikarta, Sri Ranga Sai Boyapati, Hiroki Tanaka, Robert A. May
  • Publication number: 20190206767
    Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Aleksandar ALEKSOV, Hiroki TANAKA, Robert A. MAY, Kristof DARMAWIKARTA, Changhua LIU, Chung Kwang TAN, Srinivas PIETAMBARAM, Sri Ranga Sai BOYAPATI
  • Publication number: 20190198467
    Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 27, 2019
    Inventors: Hiroki Tanaka, Aleksandar Aleksov, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta
  • Publication number: 20190198447
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
  • Publication number: 20190198436
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
  • Publication number: 20190189563
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Application
    Filed: September 29, 2016
    Publication date: June 20, 2019
    Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
  • Publication number: 20190169020
    Abstract: A package substrate is provided which comprises: one or more first conductive contacts on a first surface; one or more second conductive contacts on a second surface opposite the first surface; a dielectric layer between the first and the second surfaces; and an embedded sensing or actuating element on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded sensing or actuating element comprises a fixed metal layer in the dielectric layer and a flexible metal layer suspended over the fixed metal layer by one or more metal supports on the dielectric layer. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Applicant: Intel Corporation
    Inventors: Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Robert A. MAY, Changhua LIU, Hiroki TANAKA, Feras EID
  • Publication number: 20190111221
    Abstract: A refill assembly (129) for use in a medicinal inhaler (100). The refill assembly includes a patient port (110), and an adapter (118) configured to cause a dose of medicament to be released. The adapter is movable between a first position in which a dose of medicament is not released and a second position in which a dose of medicament is released. The refill assembly further includes a lockout member (117) movable between (i) a first (locked) position in which the adapter is not movable from its first position to its second position, and (ii) a second (unlocked) position in which the adapter is movable from its first position to its second position.
    Type: Application
    Filed: April 4, 2017
    Publication date: April 18, 2019
    Inventors: WILLIAM T. RICHARDSON, ROBERT MAY, CHRISTOPHER B.J. GROOMBRIDGE
  • Publication number: 20190111220
    Abstract: A refill assembly (129) for use in a medicinal inhaler (100). The refill assembly includes a patient port (110), and an adapter (118) configured to cause a dose of medicament to be released. The adapter is movable between a first position in which a dose of medicament is not released and a second position in which a dose of medicament is released. The refill assembly further includes a lockout mechanism positioned to lock the adapter in its first position, and a lockout override actuator (223). The lockout override actuator is movable between a first position in which the lockout mechanism is in a first locked state, and a second position in which the lockout mechanism is in a second unlocked state and the adapter is movable from its first position to its second position even when the refill assembly is not coupled to a reusable assembly.
    Type: Application
    Filed: April 4, 2017
    Publication date: April 18, 2019
    Inventors: WILLIAM T. RICHARDSON, ROBERT MAY, CHRISTOPHER B.J. GROOMBRIDGE