Abstract: A wear member that includes a pair of legs defining a slot straddles the digging edge of a piece of excavating equipment. In one construction, the slot is formed at its front end with a pair of inclined surfaces and a laterally extending ridge that is fit within a complementary channel on the digging edge. A lock is received within an opening in the wear member to releasably secure the wear member to the digging edge.

Abstract: The invention is a point-of-load power conditioning system for computer memory modules that provides regulation and fast transient response for memory integrated circuit bias voltages. The invention uses low voltage drop regulation circuitry that is physically located on individual memory modules. Power consumption and memory module regulator power dissipation are minimized by use of off-module power preconditioning that provides module input power at an optimized voltage for the on-module regulator circuitry.

Abstract: The invention is a clock interface circuit for high-speed computer memory modules. It provides improved timing margin due to improved rise and fall times than achieved with present JEDEC specified clock distribution and timing networks. The invention also provides for improved clock and inverse clock symmetry around VREF.

Abstract: The invention is an electronic circuit designed for incorporation on computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.

Abstract: A wear assembly for excavating equipment which has a wear member overlying a leading edge of the excavating equipment, a removable lock for releasably holding the wear member to the leading edge, and a stabilizer, wherein (i) the wear member has a pair of legs to straddle the leading edge with a first leg extending along a first side of the leading edge and a second leg extending along a second side of the leading edge opposite the first side, (ii) the first leg has an opening for receiving the lock and a second leg free of such locks, and (iii) the stabilizer is fixed to the second side of the leading edge and includes a holding surface to overlie a portion of the second leg to prevent the second leg from moving away from the second side of the leading edge.

Abstract: The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.

Abstract: The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflected power appearing on the isolator output. In numerous embodiments, the invention operates in circuit applications from dc through millimeter wave. Multistage electronic isolator embodiments provide increased isolation and greater noise reduction. In other embodiments, the electronic isolator also removes noise appearing on its input. In another embodiment, the invention is configured for high power applications. This embodiment includes circuitry for redirecting power away from the load into resistors or other dissipative elements. In another embodiment, the electronic isolator is configured to remove signal distortion produced by one or more power amplifiers in the system.

Abstract: The present invention is a digital to analog converter circuit that provides significantly lower distortion than achieved by digital to analog converter circuits having comparable speed and resolution utilizing the present art. The present invention provides linear or higher order transitions between clock transition time points rather than step transitions used in the present art. Distortion reduction can exceed 30 dB in the embodiment with linear sample-to-sample transitions and greater in alternate embodiments with non-linear transitions. In other embodiments, the present invention can provide low distortion at resolutions from 16 to 24 bits or more at sample rates typical of high-speed 8-bit devices of the present art.

Abstract: The present invention provides termination for transmission line structures propagating common mode signals. Common mode signals typically represent noise in systems wherein information is transmitted as differential mode signals. The present invention terminates the common mode signals in a dynamically matched termination that prevents or significantly reduces reflection of said common signals without interference with differential mode transmission lines or their normal operation. Application is shown for an unshielded, twisted pair transmission line as commonly used in telephony-based systems for both voice and broadband data communication. The methods for application of the present invention to systems with large numbers of conductors are also shown.

Abstract: The present invention is an electronic circuit that reduces crosstalk in communications systems employing twisted pair, Ethernet, polyphase or shielded wire transmission media. The present invention includes three stages of crosstalk noise reduction. Stage 1 filters common mode noise from the transmission media and balances the resistive and reactive parasitic electrical characteristics of the transmission media that couple each line to the local ground over the operating frequency band. The second Stage performs differential crosstalk noise reduction in real time using multiple feedback loops. It can dynamically locate and set optimal system operating conditions for minimal differential crosstalk coupling for the specific environmental and interfering channel utilization conditions. The third Stage utilizes digital signal processing techniques to further reduce any residual crosstalk after analog-to-digital conversion.