Abstract: A separator for a gas stream has a horizontal tank with a fluid inlet, a fluid outlet and a flow path along the inside of the horizontal tank. A flow barrier is disposed within the tank between the inlet and the outlet. One or more sets of liquid ports are in fluid communication with the tank and positioned at a bottom surface of the tank. Each set of liquid outlets has a first port and a second port. The first port is positioned upstream along the flow path relative to the second port. A fluid passage is in fluid communication with the first port and the second port. The fluid passage defines a secondary flow path adjacent to the horizontal tank, where the first port acts as a draft inlet to the secondary flow path and the second port acts as a draft outlet from the secondary flow path to the tank.

Abstract: A separator for a wet gas stream has an upper section having an outer peripheral wall, a top, and a bottom perforated baffle. A cone-shaped baffle is positioned on the perforated bottom baffle and extending toward the inlet in the top of the upper section. A spiral baffle has a bottom edge adjacent to the cone-shaped baffle and a top edge adjacent to the top of the upper section. The spiral baffle defines a curved flow path between the inlet and the outlet of the upper portion. A vortex flow section is defined by the cone-shaped baffle and the outer peripheral wall. The vortex flow section is fed by the curved flow path defined by the cone-shaped baffle. A lower section is below the perforated baffle. The lower section has a gas outlet and a liquid outlet.

Abstract: A separator for a gas stream has a horizontal tank with a fluid inlet, a fluid outlet and a flow path along the inside of the horizontal tank. A flow barrier is disposed within the tank between the inlet and the outlet. One or more sets of liquid ports are in fluid communication with the tank and positioned at a bottom surface of the tank. Each set of liquid outlets has a first port and a second port. The first port is positioned upstream along the flow path relative to the second port. A fluid passage is in fluid communication with the first port and the second port. The fluid passage defines a secondary flow path adjacent to the horizontal tank, where the first port acts as a draft inlet to the secondary flow path and the second port acts as a draft outlet from the secondary flow path to the tank.

Abstract: There is provided a separator for a gas stream. The separator has a vertical tank having a side wail, a top and a bottom. The tank has an inlet, a gas outlet, and a liquid outlet, the liquid outlet being located at the bottom of the tank.

Abstract: An assembly may include a fitting, a first pipe, and a first seal. The fitting may include an annular body having a first insertion end and an inner diametrical surface having a first knurled portion disposed adjacent the first insertion end. The first pipe may include a first end portion that is received into the first insertion end of the body and an outer diametrical surface including knurls formed thereon. The knurls of the outer diametrical surface may engage the first knurled portion of the fitting. The first seal element may be disposed within the fitting and may sealingly engage the first pipe and the fitting body. The engagement between the inner diametrical surface of the fitting and the outer diametrical surface of the pipe may a press fit and/or an interference fit.

Abstract: A separator for a wet gas stream has an upper section having an outer peripheral wall, a top, and a bottom perforated baffle. A cone-shaped baffle is positioned on the perforated bottom baffle and extending toward the inlet in the top of the upper section. A spiral baffle has a bottom edge adjacent to the cone-shaped baffle and a top edge adjacent to the top of the upper section. The spiral baffle defines a curved flow path between the inlet and the outlet of the upper portion. A vortex flow section is defined by the cone-shaped baffle and the outer peripheral wall. The vortex flow section is fed by the curved flow path defined by the cone-shaped baffle. A lower section is below the perforated baffle. The lower section has a gas outlet and a liquid outlet.

Abstract: A separator for a wet gas stream has an upper conduit having an inlet, an outlet and an outer peripheral wall. A helical baffle is positioned within the upper conduit defining a helical flow path. The helical flow path generates a vortex in gas flowing through the upper conduit, such that liquids in the gas stream move toward the outer peripheral wall. A lower conduit has an input in axial alignment with the outlet of the upper conduit and an outlet. The input of the lower conduit and the output of the upper conduit are separated by a gap, such that liquids are ejected from the upper conduit without entering the lower conduit, and such that the gas stream within the upper conduit is transferred to the lower conduit.

Abstract: An assembly may include a fitting, a first pipe, and a first seal. The fitting may include an annular body having a first insertion end and an inner diametrical surface having a first knurled portion disposed adjacent the first insertion end. The first pipe may include a first end portion that is received into the first insertion end of the body and an outer diametrical surface including knurls formed thereon. The knurls of the outer diametrical surface may engage the first knurled portion of the fitting. The first seal element may be disposed within the fitting and may sealingly engage the first pipe and the fitting body. The engagement between the inner diametrical surface of the fitting and the outer diametrical surface of the pipe may a press fit and/or an interference fit.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.

Abstract: A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.

Abstract: A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.

Abstract: A memory system circuit and method therefor are included. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.

Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

Abstract: A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.

Abstract: A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.

Abstract: A disk drive includes a slider assembly and a controller that directs current to the slider assembly to dynamically adjust the head-to-disk spacing. In one embodiment, the slider assembly includes a write element having a first end, a second end and an intermediate section, a conductor that is connected to the intermediate section. In this embodiment, the controller directs electrical current through the conductor to heat the write element without writing data to a storage disk. The electrical current can be directed through the conductor at any time prior to data transfer or during data transfer. Heating the write element causes a deformation of the slider assembly to decrease the head-to-disk spacing. In another embodiment, the slider assembly includes a separate slider deformer. Electrical current is selectively directed to the slider deformer to cause a deformation of the slider assembly to obtain a desired head-to-disk spacing.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.