Abstract: A method and apparatus for interference cancellation in a high-speed modem that includes a first coupler for receiving a differential signal including a received data signal, a second coupler for deriving a common mode signal for the transmitted signal, and a phase-shift circuit coupled to the second coupler for deriving orthogonal signals from the common mode signal. First and second multipliers mix the orthogonal signals with the received signal. First, second, and third integrators integrate the mixed orthogonal signals and the common mode signal to produce orthogonal signal level measurements ITONE and QTONE and a common mode signal level measurement CMTONE, respectively. A controller derives orthogonal correction signals from measurements by dividing ITONE and QTONE respectively by CMTONE and multiplying by an appropriate constant. This output is then used to increment or decrement the signals to the respective digital to analog converters, DACI and DACQ.

Abstract: A double balanced mixer consisting of two complementary solid state switches, with a high reverse-bias voltage provided by isolating the sides of the complementary solid state switches receiving the carrier signal from one another, and connecting the other sides together. If the solid state switches are designed to couple the input signal to the output signal in response to the carrier signal having an amplitude of zero volts, then a solid state switch in forward-bias will have a potential of zero volts on both sides of it. While this solid state switch is in forward-bias, the second solid state switch will be receiving the complementary carrier signal on one side, which is a high positive voltage, and zero volts on the side connected to the first solid state switch. The second solid state switch will therefore see a reverse-bias potential difference equal to the potential difference between the positive voltage of the complementary carrier signal and zero volts.

Abstract: A clock recovery circuit includes a resonant circuit which has a varactor diode and is driven into oscillation at a variable frequency in response to a control voltage fed to the varactor diode. Basically, the resonant circuit is tuned into the clock frequency of an incoming binary data signal. The clock recovery circuit provides a clock signal which is associated with a data output signal. The desired transition timing of the clock signal is at mid-point of the incoming binary data signal. When the transition timing is advanced or delayed from the mid-point due to changes in the resonant frequency of the circuit, the control voltage changes, with the result that the tuning frequency of the resonant circuit is varied. In response to the change of the resonant frequency, the transition timing of the clock output signal is delayed or advanced. This condition is detected and the control voltage fed to the varactor is changed, resulting in achievement of correct transition timing.