Patents by Inventor Robert McMorrow
Robert McMorrow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10855383Abstract: A system and a method for calibrating an antenna using trim bits and non-volatile memory is disclosed. In one aspect, an apparatus includes a power amplifier configured to at least amplify the output signal of the first antenna. The power amplifier includes multiple stages. The apparatus further includes a trim control circuit configured to adjust a bias of one of the stages of the power amplifier, using trim bits from non-volatile memory. The trim control circuit is further configured to scale the bias of one of the plurality of stages of the power amplifier by an integer between 0 and 2n?1 corresponding to a binary number formed by the first plurality of trim bits, wherein n corresponds to the number of trim bits.Type: GrantFiled: March 14, 2019Date of Patent: December 1, 2020Assignee: ANOKIWAVE, INC.Inventors: Robert McMorrow, Vipul Jain, Mikhail Shirokov, Kevin B. Greene, Susanne A. Paul, Shamsun Nahar
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Publication number: 20200295853Abstract: A system and a method for calibrating an antenna using trim bits and non-volatile memory is disclosed. In one aspect, an apparatus includes a power amplifier configured to at least amplify the output signal of the first antenna. The power amplifier includes multiple stages. The apparatus further includes a trim control circuit configured to adjust a bias of one of the stages of the power amplifier, using trim bits from non-volatile memory. The trim control circuit is further configured to scale the bias of one of the plurality of stages of the power amplifier by an integer between 0 and 2n-1 corresponding to a binary number formed by the first plurality of trim bits, wherein n corresponds to the number of trim bits.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: ANOKIWAVE, INC.Inventors: Robert McMorrow, Vipul Jain, Mikhail Shirokov, Kevin B. Greene, Susanne A. Paul, Shamsun Nahar
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Patent number: 10608756Abstract: A system and a method for calibrating an output signal of an antenna is disclosed. In one aspect, an apparatus includes a first digital adder configured to generate a gain offset by at least adding gain calibration data from non-volatile memory and gain command data from static memory. The apparatus further includes an amplitude gain circuit configured to modify, based at least in part on the gain offset, an amplitude of a first output signal of a first antenna. The modified amplitude of the first output signal is provided to enable pre-calibration of the first output signal. The apparatus further includes a power detector configured to measure an output power of the first output signal. The apparatus further includes at least one processor configured to generate a difference between the measured and expected output power, and adjust gain command data in response to the generated difference.Type: GrantFiled: September 5, 2018Date of Patent: March 31, 2020Assignee: ANOKIWAVE, INC.Inventors: Vipul Jain, Robert Ian Gresham, Robert McMorrow, David Warren Corman, Nitin Jain
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Publication number: 20200076515Abstract: A system and a method for calibrating an output signal of an antenna is disclosed. In one aspect, an apparatus includes a first digital adder configured to generate a gain offset by at least adding gain calibration data from non-volatile memory and gain command data from static memory. The apparatus further includes an amplitude gain circuit configured to modify, based at least in part on the gain offset, an amplitude of a first output signal of a first antenna. The modified amplitude of the first output signal is provided to enable pre-calibration of the first output signal. The apparatus further includes a power detector configured to measure an output power of the first output signal. The apparatus further includes at least one processor configured to generate a difference between the measured and expected output power, and adjust gain command data in response to the generated difference.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Inventors: Vipul Jain, Robert Ian Gresham, Robert McMorrow, David Warren Corman, Nitin Jain
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Patent number: 10559879Abstract: An active electronic steered antenna (AESA) circuit monitors bursts of a phased array that has a plurality of signal chains. Each signal chain therefore has a burst output for transmitting at least one burst. To monitor bursts, the AESA circuit has an input that is operably couplable with the burst output of at least one signal chain of the phased array. The input is configured to receive one or more bursts transmitted by the burst output(s) of the at least one signal chain. The AESA circuit also has a sample circuit operably coupled with the input and configured to sample the one or more bursts to produce one or more corresponding samples, and memory operably coupled with the sample circuit. The memory receives and stores the one or more samples. To provide access to the samples, the AESA circuit also has a memory interface.Type: GrantFiled: July 18, 2016Date of Patent: February 11, 2020Assignee: Anokiwave, Inc.Inventors: Wade Allen, Robert McMorrow, David Corman
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Patent number: 10263650Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.Type: GrantFiled: January 2, 2018Date of Patent: April 16, 2019Assignee: ANOKIWAVE, INC.Inventors: David Warren Corman, Robert McMorrow, Andrew Street, Vipul Jain, Kristian Madsen, Robert Ian Gresham, Jonathan Comeau, Gaurav Menon, Nitin Jain
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Patent number: 10224627Abstract: An apparatus may include a plurality of antenna elements forming an antenna array. The apparatus may further include a beamformer that determines one or more of phase and amplitude shifts to cause the plurality of antenna elements to produce a beam in the direction of a target. The apparatus may further include a null limiter comprising dither circuits. The dither circuits may dither the one or more of phase and amplitude shifts by adding noise to cause a side lobe of the beam to increase above a threshold value. The dither circuits may be enabled by a control signal, and the dithered one or more of phase and amplitude shifts may be provided to the antenna elements to produce the beam in the direction of the target with the side lobes above the threshold value.Type: GrantFiled: December 11, 2015Date of Patent: March 5, 2019Assignee: ANOKIWAVE, INC.Inventors: W. Timothy Carey, Nitin Jain, Robert McMorrow, David Warren Corman
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Publication number: 20180234121Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.Type: ApplicationFiled: January 2, 2018Publication date: August 16, 2018Inventors: David Warren Corman, Robert McMorrow, Andrew Street, Vipul Jain, Kristian Madsen, Robert Ian Gresham, Jonathan Comeau, Gaurav Menon, Nitin Jain
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Patent number: 9876514Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.Type: GrantFiled: August 31, 2016Date of Patent: January 23, 2018Assignee: ANOKIWAVE, INC.Inventors: David Warren Corman, Robert McMorrow, Andrew Street, Vipul Jain, Kristian Madsen, Robert Ian Gresham, Jonathan Comeau, Gaurav Menon, Nitin Jain
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Publication number: 20180019517Abstract: An active electronic steered antenna (AESA) circuit monitors bursts of a phased array that has a plurality of signal chains. Each signal chain therefore has a burst output for transmitting at least one burst. To monitor bursts, the AESA circuit has an input that is operably couplable with the burst output of at least one signal chain of the phased array. The input is configured to receive one or more bursts transmitted by the burst output(s) of the at least one signal chain. The AESA circuit also has a sample circuit operably coupled with the input and configured to sample the one or more bursts to produce one or more corresponding samples, and memory operably coupled with the sample circuit. The memory receives and stores the one or more samples. To provide access to the samples, the AESA circuit also has a memory interface.Type: ApplicationFiled: July 18, 2016Publication date: January 18, 2018Inventors: Wade Allen, Robert McMorrow, David Corman
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Publication number: 20170170556Abstract: An apparatus may include a plurality of antenna elements forming an antenna array. The apparatus may further include a beamformer that determines one or more of phase and amplitude shifts to cause the plurality of antenna elements to produce a beam in the direction of a target. The apparatus may further include a null limiter comprising dither circuits. The dither circuits may dither the one or more of phase and amplitude shifts by adding noise to cause a side lobe of the beam to increase above a threshold value. The dither circuits may be enabled by a control signal, and the dithered one or more of phase and amplitude shifts may be provided to the antenna elements to produce the beam in the direction of the target with the side lobes above the threshold value.Type: ApplicationFiled: December 11, 2015Publication date: June 15, 2017Inventors: W. Timothy Carey, Nitin Jain, Robert McMorrow, David Warren Corman
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Publication number: 20050014473Abstract: A high performance single-pole-double-throw (SPDT) Transmitter/Receiver (T/R) FET switch utilizes a plurality of multi-gate FETs in series to realize low insertion loss, low harmonic distortion and high power handling capabilities. The SPDT switch consists of an antenna port, a transmitter branch coupled to a transmitter port through a plurality of multi-gate FETs in series and a receiver branch coupled to a receiver port through a plurality of multi-gate FETs in series. When a high power signal passes from the transmitter port to the antenna port through the transmitter branch, the receiver branch is required to be shut off electrically to prevent the high power signal from leaking to receiver port. This leakage can degrade the isolation of the switch and cause harmonic distortion. Furthermore, the transmitter branch is required to provide a resistance as small as possible to reduce the power loss when it passes through the transmitter branch to the antenna port.Type: ApplicationFiled: July 16, 2003Publication date: January 20, 2005Inventors: Yibing Zhao, Shuyun Zhang, Robert McMorrow