Patents by Inventor Robert McNeill NORTON-WRIGHT

Robert McNeill NORTON-WRIGHT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12039170
    Abstract: A hardware revocation engine for invalidating a pointer, that refers to a deallocated object, from memory in a memory constrained system. The hardware revocation engine has a revocation pipeline coupled to a pipeline of a main processor of the memory constrained system. The revocation pipeline shares access to memory with the main pipeline, the revocation pipeline comprising at least a first stage and a subsequent second stage. In a first cycle of the revocation pipeline, the first stage of the revocation pipeline loads a first pointer-sized value from the memory. In a second cycle: the second stage checks whether the first loaded pointer-sized value is a pointer referring to deallocated memory. In a third cycle: in response to the outcome of the check indicating that the first loaded pointer-sized value is a pointer referring to deallocated memory, the first stage invalidates the first pointer-sized value.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: July 16, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Thomas Chisnall, Hongyan Xia, Nathaniel Wesley Filardo, Robert McNeill Norton-Wright
  • Publication number: 20230393746
    Abstract: A hardware revocation engine for invalidating a pointer, that refers to a deallocated object, from memory in a memory constrained system. The hardware revocation engine has a revocation pipeline coupled to a pipeline of a main processor of the memory constrained system. The revocation pipeline shares access to memory with the main pipeline, the revocation pipeline comprising at least a first stage and a subsequent second stage. In a first cycle of the revocation pipeline, the first stage of the revocation pipeline loads a first pointer-sized value from the memory. In a second cycle: the second stage checks whether the first loaded pointer-sized value is a pointer referring to deallocated memory. In a third cycle: in response to the outcome of the check indicating that the first loaded pointer-sized value is a pointer referring to deallocated memory, the first stage invalidates the first pointer-sized value.
    Type: Application
    Filed: September 22, 2022
    Publication date: December 7, 2023
    Inventors: David Thomas CHISNALL, Hongyan XIA, Nathaniel Wesley FILARDO, Robert McNeill NORTON-WRIGHT
  • Publication number: 20230029331
    Abstract: In examples there is a computing device comprising a processor, the processor having a memory management unit. The computing device also has a memory that stores instructions that, when executed by the processor, cause the memory management unit to receive a memory access instruction comprising a virtual memory address; translate the virtual memory address to a physical memory address of the memory, and obtain permission information associated with the physical memory address. Responsive to the permission information indicating that metadata is permitted to be associated with the physical memory address, a check is made of a metadata summary table stored in the physical memory to check whether metadata is compatible with the physical memory address. Responsive to the check being unsuccessful, a trap is sent to system software of the computing device in order to trigger dynamic allocation of physical memory for storing metadata associated with the physical memory address.
    Type: Application
    Filed: July 26, 2021
    Publication date: January 26, 2023
    Inventors: David Thomas CHISNALL, Nathaniel Wesley FILARDO, Robert McNeill NORTON-WRIGHT