Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract: Methodologies and an apparatus for enabling scatterometry to be used to estimate dimensions of fabricated semiconductor devices are provided. Embodiments include initiating scatterometry on a fabricated test structure comprising a two-dimensional array of features, each of the features being horizontally separated from an adjacent one of the features by a narrow trench region extending a first distance in a horizontal direction and each of the features being vertically separated from an adjacent one of the features by an isolated trench region extending a second distance in a vertical direction. A scattering spectra corresponding to one or more physical characteristics of the fabricated test structure based on results of the scatterometry is determined. The scattering spectra is associated with the one or more physical characteristics in a library for estimating at least one physical dimension of a fabricated structure.

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.