Patents by Inventor Robert Menezes
Robert Menezes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220200602Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.Type: ApplicationFiled: July 30, 2021Publication date: June 23, 2022Applicant: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
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Publication number: 20220190831Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.Type: ApplicationFiled: March 8, 2022Publication date: June 16, 2022Applicant: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Guarav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11296708Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.Type: GrantFiled: December 21, 2020Date of Patent: April 5, 2022Assignee: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11290111Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.Type: GrantFiled: May 21, 2021Date of Patent: March 29, 2022Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11290112Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.Type: GrantFiled: May 21, 2021Date of Patent: March 29, 2022Assignee: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11283453Abstract: An adder with first and second majority gates is provided. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.Type: GrantFiled: December 21, 2020Date of Patent: March 22, 2022Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11277137Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.Type: GrantFiled: May 21, 2021Date of Patent: March 15, 2022Assignee: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11165430Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.Type: GrantFiled: December 21, 2020Date of Patent: November 2, 2021Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Publication number: 20210226636Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.Type: ApplicationFiled: December 21, 2020Publication date: July 22, 2021Applicant: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Guarav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Publication number: 20210203324Abstract: An adder with first and second majority gates is provided. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.Type: ApplicationFiled: December 21, 2020Publication date: July 1, 2021Applicant: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Publication number: 20210203326Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.Type: ApplicationFiled: February 23, 2021Publication date: July 1, 2021Applicant: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Publication number: 20210203325Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.Type: ApplicationFiled: December 21, 2020Publication date: July 1, 2021Applicant: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11025254Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.Type: GrantFiled: February 20, 2020Date of Patent: June 1, 2021Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11018672Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.Type: GrantFiled: December 27, 2019Date of Patent: May 25, 2021Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11012076Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.Type: GrantFiled: February 21, 2020Date of Patent: May 18, 2021Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 10951213Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.Type: GrantFiled: February 21, 2020Date of Patent: March 16, 2021Assignee: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 10944404Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.Type: GrantFiled: December 27, 2019Date of Patent: March 9, 2021Assignee: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 9162756Abstract: A landing gear (10), including: a bogie beam (12); an axle (14) pivotally connected to the bogie beam (12); a locking member (40) coupled to the axle (14) such that movement of the axle (14) invokes movement of the locking member (40), said movement of the locking member (40) defining a swept volume; and a locking mechanism (60) coupled to the bogie beam (12) and including first (65a) and second glide members, (65a, 65b) the locking mechanism (60) being arranged to move the glide members (65a, 65b) between locking positions, where glide members (65a, 65b) are within the swept volume on opposing sides of the locking member (40) and in which position the locking mechanism (60) is arranged to lock the locking member (40) in a predetermined position, and non-locking positions, where the locking mechanism (60) is arranged permit movement of the locking member (40).Type: GrantFiled: May 19, 2011Date of Patent: October 20, 2015Assignee: Messier-Dowty LimitedInventors: Robert Menezes, Matthew Hilliard, Peter Michaelides
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Patent number: 8608105Abstract: There is described a landing gear having a bogie including a elongated beam (2) for accommodating at least two axles receiving each a pair of ground engaging wheels, at least one axle (5) being pivotally mounted on the elongated beam. The landing gear further includes axle travel limitation means (10) extending between said pivotable axle and said elongated beam to be hitched up thereto, said travel limitation means being deformable one way starting from an stable and lockable state thereof corresponding to a landing position of said pivotable axle. There are also described independently lockable and actuatable telescopic struts.Type: GrantFiled: February 10, 2010Date of Patent: December 17, 2013Assignee: Messier-Dowty LtdInventors: Ian Robert Bennett, Robert Menezes, Paul Shaw
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Publication number: 20130161445Abstract: There is described a landing gear having a bogie including a elongated beam (2) for accommodating at least two axles receiving each a pair of ground engaging wheels, at least one axle (5) being pivotally mounted on the elongated beam. The landing gear further includes axle travel limitation means (10) extending between said pivotable axle and said elongated beam to be hitched up thereto, said travel limitation means being deformable one way starting from an stable and lockable state thereof corresponding to a landing position of said pivotable axle. There are also described independently lockable and actuatable telescopic struts.Type: ApplicationFiled: February 10, 2010Publication date: June 27, 2013Applicant: MESSIER-DOWTY LTDInventors: Ian BENNETT, Robert MENEZES, Paul SHAW