Abstract: Clock data recovery broadcast for multi-lane SerDes is disclosed. In some implementations, a serial input/output (I/O) interface includes a master lane and a plurality of slave lanes to receive serial incoming data. The master lane has a master clock and data recovery (CDR) module to generate master data sample clock control signals. The master data sample clock control signals can be broadcasted to the slave lanes. Furthermore, each of the plurality of slave lanes having a slave CDR module. The slave CDR module can include a clock edge tracking module to generate local data sample clock control signals, and a multiplexer to select the master data sample clock control signals or local data sample clock control signals to apply in the respective slave lane in response to a signal from a CDR controller indicative of a low power mode.

Abstract: Clock data recovery broadcast for multi-lane SerDes is disclosed. In some implementations, a serial input/output (I/O) interface includes a master lane and a plurality of slave lanes to receive serial incoming data. The master lane has a master clock and data recovery (CDR) module to generate master data sample clock control signals. The master data sample clock control signals can be broadcasted to the slave lanes. Furthermore, each of the plurality of slave lanes having a slave CDR module. The slave CDR module can include a clock edge tracking module to generate local data sample clock control signals, and a multiplexer to select the master data sample clock control signals or local data sample clock control signals to apply in the respective slave lane in response to a signal from a CDR controller indicative of a low power mode.

Abstract: Systems and methods to provide a low-power mode for serial links are disclosed. One embodiment of such a system includes a transmitter coupled to a link; a receiver coupled to the link and configured to receive signals over the link from the transmitter; a transmit control module configured to cause the transmitter to enter and exit a low-power mode; and a clock module coupled to the transmitter and configured to provide a clock signal to the transmitter, wherein the clock module is further configured to provide the clock signal as a divided clock signal to the transmitter when the transmitter is in the low-power mode, further wherein the divided clock signal has a same phase as the clock signal before entry into the low-power mode.

Abstract: Systems and methods to provide a low-power mode for serial links are disclosed. One embodiment of such a system includes a transmitter coupled to a link; a receiver coupled to the link and configured to receive signals over the link from the transmitter; a transmit control module configured to cause the transmitter to enter and exit a low-power mode; and a clock module coupled to the transmitter and configured to provide a clock signal to the transmitter, wherein the clock module is further configured to provide the clock signal as a divided clock signal to the transmitter when the transmitter is in the low-power mode, further wherein the divided clock signal has a same phase as the clock signal before entry into the low-power mode.

Abstract: An apparatus for setting the timing of a triggering edge of a clock signal with respect to received parallel data. The apparatus includes a set of flip-flops including respective data inputs, respective clock inputs, and respective data outputs, wherein the set of flip-flops are configured to generate a set of output data at the data output based on parallel data applied to the respective data inputs in response to a triggering edge of a clock signal applied to the clock inputs; a variable delay element configured to apply a calibrated delay to the clock signal; and a controller configured to generate a control signal for the variable delay element to apply the calibrated delay to the clock signal based on the set of output data generated at the data outputs of the set of flip-flops.

Abstract: An apparatus for setting the timing of a triggering edge of a clock signal with respect to received parallel data. The apparatus includes a set of flip-flops including respective data inputs, respective clock inputs, and respective data outputs, wherein the set of flip-flops are configured to generate a set of output data at the data output based on parallel data applied to the respective data inputs in response to a triggering edge of a clock signal applied to the clock inputs; a variable delay element configured to apply a calibrated delay to the clock signal; and a controller configured to generate a control signal for the variable delay element to apply the calibrated delay to the clock signal based on the set of output data generated at the data outputs of the set of flip-flops.

Abstract: A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.

Abstract: A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.

Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.

Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.

Abstract: A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing.

Abstract: An adder which takes advantage of the early arriving bits of a time skewed operand to provide a result to an add or substract operation without additional latency. Possible partial results are calculated and then selectively combined according to the late arriving data as the late arriving data becomes available. In an embodiment of the present invention, a first operand is partitioned into groups according to the arrival time of the skewed data, and possible partial results for each group are calculated for the full range of partial inputs that affect it. In addition, the high order groups are calculated with and without a borrow (carry) which is propagated from a low order group. Once the delayed partial operands are known and the borrows (carrys) determined the partial results are gated through multiplexers according to the borrows and partial results, and thus the result is provided with a delay similar to the delay in arrival of the skewed operand.