Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating manifests with the client configurable logic for various purposes.

Abstract: A controller is configured to transmit a broadcast write request on at least one bus. The broadcast write request includes an address and a value. A first logic module determines that the broadcast write request is targeting the first logic module. The first logic module stores the value at a first addressed register specified by the register address. The second logic module determines that the broadcast write request is targeting the second logic module. The second logic module stores the value at a second addressed register specified by the register address. The first and second logic modules are connected to the at least one bus.

Abstract: A bus controller is configured to transmit a broadcast read request on at least one bus. The broadcast read request includes an address. A first logic module determines that the broadcast read request is targeting the first logic module. The first logic module reads a first value from a first register included in the first logic module. The first register is specified by the address included in the broadcast read request. The first value is transmitted onto the at least one bus. A second logic module determines that the broadcast read request is targeting the second logic module. The second logic module reads a second value from a second register included in the second logic module. The second register is specified by the address included in the broadcast read request. The second value is transmitted onto the at least one bus.

Abstract: Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may implement processes to manage write requests in a general and flexible manner. The I/O adapter device may also implement processes to manage write requests in a fast an efficient—that is, low latency—manner. Low latency write requests processes may include determining that a write packet for a write request can be processed without additional assistance from a processor, once a processor has initiated a memory access request to fetch write data and also generated protocol information for transmitting the write packet. The I/O adapter device may then process and transmit the write packet through an offload pipeline, without interrupting a processor.

Abstract: A computing system can include a server computer and a configurable hardware platform. The server computer can include instances or domains such as a management partition and a user partition. The management partition can be used to perform management services for the user partitions and the configurable hardware platform. The configurable hardware platform is coupled to the server computer, and can include a host logic and a configurable application logic. In an embodiment, the computing system is configured to provide the user partition with physical or virtual access to a first part of the configurable hardware platform through the host logic in the configurable hardware platform. The computing system is also configured to provide the user partition with virtual access to certain portions/resources associated with the configurable hardware platform.

Abstract: Server computers often include one or more input/output (I/O) devices for communicating with a network or direct attached storage device. Data written to or read from storage devices may acquire errors in transit. The I/O adapter device may implement processes to generate or check error correction values, where the error correction values are provided to verify the correctness of the written or read value. The I/O adapter device may determine the portion of the data to be used in calculating the error correction value in a flexible and configurable manner.

Abstract: A host device can offload certain copy operations to an I/O adapter device coupled to the host device. The I/O adapter device can perform a copy operation to copy data from a source storage volume to a destination storage volume. The source storage volume and the destination storage volume can be local or remote to the I/O adapter device. The copy operations can be performed for replica creation, online migration or for copy-on-write snapshots.

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

Abstract: In a multi-tenant environment, separate virtual machines can be used for configuring and operating different subsets of programmable integrated circuits, such as a Field Programmable Gate Array (FPGA). The programmable integrated circuits can communicate directly with each other within a subset, but cannot communicate between subsets. Generally, all of the subsets of programmable ICs are within a same host server computer within the multi-tenant environment, and are sandboxed or otherwise isolated from each other so that multiple customers can share the resources of the host server computer without knowledge or interference with other customers.

Abstract: Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may have limited physical resources, such as memory. Large I/O transactions may occupy all available memory on the I/O adapter device, thus causing other I/O transactions to experience intermittent and excessive delays. The I/O adapter device can be configured to issue one or more transactions for a large I/O request. Each transaction transfers a portion of the data requested by the large I/O request. When all the transactions have completed, the client that requested the large I/O request is informed that the I/O request has completed.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may implement processes to manage write requests in a general and flexible manner. The I/O adapter device may also implement processes to manage write requests in a fast an efficient—that is, low latency—manner. Low latency write requests processes may include determining that a write packet for a write request can be processed without additional assistance from a processor, once a processor has initiated a memory access request to fetch write data and also generated protocol information for transmitting the write packet. The I/O adapter device may then process and transmit the write packet through an offload pipeline, without interrupting a processor.

Abstract: Server computers often include one or more input/output (I/O) devices for communicating with a network or directly attached storage device. Data transferred between these devices may include blocks of data with a common often repeated and identifiable data pattern. Transfer and storage of data of this nature may be optimized by transferring primarily blocks of data that are not of the pre-determined data pattern. An indicator may be transferred and stored with transferred data that has been reduced in size in this manner.

Abstract: Server computers often include one or more input/output (I/O) adapter devices for communicating with a network or directly attached storage device. The data transfer latency for request can be reduced by utilizing ingress data placement logic to bypass the processor of the I/O adapter device. For example, host memory descriptors can be stored in a content addressable memory unit of the I/O adapter device to facilitate placement of requested data.

Abstract: Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may have limited physical resources, such as memory. Large I/O transactions may occupy all available memory on the I/O adapter device, thus causing other I/O transactions to experience intermittent and excessive delays. The I/O adapter device can be configured to issue one or more transactions for a large I/O request. Each transaction transfers a portion of the data requested by the large I/O request. When all the transactions have completed, the client that requested the large I/O request is informed that the I/O request has completed.

Abstract: This invention provides a means of protecting power dissipating pass elements from exceeding their predetermined thermal limits. In one preferred embodiment, the circuit protects a pass element in a battery charging circuit from exceeding its threshold junction temperature by predicting temperature based upon the voltage across the pass element and the current flowing through it. From this predicted temperature, current is reduced to provide charging of a battery at a constant power. The circuit includes a voltage sensing circuit and a plurality of comparators for selecting a predetermined current based upon the output of the voltage sensing circuit. The circuit provides a piecewise linear approximation of proper pass element voltage and current values to maintain a suitable threshold junction temperature.