Patents by Inventor Robert Michael Vyne

Robert Michael Vyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9514927
    Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 6, 2016
    Assignee: ASM IP HOLDING B.V.
    Inventors: John Tolle, Matthew G. Goodman, Robert Michael Vyne, Eric R. Hill
  • Publication number: 20160254137
    Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.
    Type: Application
    Filed: March 28, 2016
    Publication date: September 1, 2016
    Inventors: John Tolle, Matthew G. Goodman, Robert Michael Vyne, Eric R. Hill
  • Patent number: 9299557
    Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 29, 2016
    Assignee: ASM IP HOLDING B.V.
    Inventors: John Tolle, Matthew G. Goodman, Robert Michael Vyne, Eric R. Hill
  • Publication number: 20150270122
    Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: ASM IP HOLDING B.V.
    Inventors: John Tolle, Matthew G. Goodman, Robert Michael Vyne, Eric R. Hill
  • Patent number: 6126744
    Abstract: A method to prepare thermal reactors for operation after installation, modification, upgrade and routine preventive maintenance operations. Variations in reaction rate across a wafer surface are used to determine corresponding variations in surface temperature across the wafer surface. Surface temperature variations results in thickness variations of a chemically deposited layer. For selected thicknesses, a chemically deposited layer is transparent and exhibits color variations corresponding to the thickness variations that result from the surface temperature variations. These color variations are then correlated to surface temperature variations to enable wafer heating adjustments to reduce surface temperature variations.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: October 3, 2000
    Assignee: ASM America, Inc.
    Inventors: Mark Richard Hawkins, Robert Michael Vyne, Cornelius Alexander van der Jeugd