Abstract: A method for making a semiconductor device may include, in an epitaxial deposition tool, performing an anneal on a semiconductor on insulator (SOI) substrate including a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness. The method may also include, in the epitaxial deposition tool, performing an in-situ etch to reduce the second semiconductor layer to a second thickness less than the first thickness, and forming a superlattice layer on the second semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a semiconductor device may include, in an epitaxial deposition tool, performing an anneal on a semiconductor on insulator (SOI) substrate including a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness. The method may also include, in the epitaxial deposition tool, performing an in-situ etch to reduce the second semiconductor layer to a second thickness less than the first thickness, and forming a superlattice layer on the second semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a semiconductor device may include, in an epitaxial deposition tool, performing an anneal on a semiconductor on insulator (SOI) substrate including a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness. The method may also include, in the epitaxial deposition tool, performing an in-situ etch to reduce the second semiconductor layer to a second thickness less than the first thickness, and forming a superlattice layer on the second semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: A method to prepare thermal reactors for operation after installation, modification, upgrade and routine preventive maintenance operations. Variations in reaction rate across a wafer surface are used to determine corresponding variations in surface temperature across the wafer surface. Surface temperature variations results in thickness variations of a chemically deposited layer. For selected thicknesses, a chemically deposited layer is transparent and exhibits color variations corresponding to the thickness variations that result from the surface temperature variations. These color variations are then correlated to surface temperature variations to enable wafer heating adjustments to reduce surface temperature variations.