Patents by Inventor Robert Michael Walker
Robert Michael Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8171211Abstract: A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.Type: GrantFiled: March 9, 2011Date of Patent: May 1, 2012Assignee: QUALCOMM IncorporatedInventor: Robert Michael Walker
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Patent number: 8122187Abstract: A memory system, and process for refreshing the memory, is disclosed. The memory system includes memory, a temperature sensor configured to measure the temperature of the memory, and a memory controller configured to refresh the memory at a refresh rate, the refresh rate being controlled as a function of the temperature measured by the temperature sensor.Type: GrantFiled: June 10, 2005Date of Patent: February 21, 2012Assignee: QUALCOMM IncorporatedInventors: Robert Michael Walker, Perry Willmann Remaklus, Jr.
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Publication number: 20110161579Abstract: A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Applicant: QUALCOMM INCORPORATEDInventor: Robert Michael Walker
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Patent number: 7953921Abstract: In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon entering DARF mode. The memory refreshes the currently addressed bank in response to a DARF command, and increments the bank address counter in a predetermined sequence. The controller tracks the bank address, and may issue one or more memory access commands while a DARF operation is being performed, if the memory access and the refresh are directed to different banks. Upon exiting a self-refresh mode, the bank address counter assumes a second predetermined value. The second predetermined value may be fixed, or may be n+1, where n is the value of the bank address counter when self-refresh mode is initiated.Type: GrantFiled: April 27, 2005Date of Patent: May 31, 2011Assignee: QUALCOMM IncorporatedInventors: Robert Michael Walker, Perry Willmann Remaklus, Jr.
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Patent number: 7930471Abstract: A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.Type: GrantFiled: November 24, 2004Date of Patent: April 19, 2011Assignee: QUALCOMM IncorporatedInventor: Robert Michael Walker
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Patent number: 7650481Abstract: A memory system is disclosed in which the access speed may be adjusted. The memory system may include memory and a memory controller. The memory controller may be configured to generate a plurality of control signals to access the memory, and adjust the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system.Type: GrantFiled: November 24, 2004Date of Patent: January 19, 2010Assignee: QUALCOMM IncorporatedInventor: Robert Michael Walker
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Patent number: 7640392Abstract: Data not stored in the DRAM array of a SDRAM module, such as the output of a temperature sensor, are read from the SDRAM in a synchronous read cycle that is seamlessly interspersed with SDRAM read and write cycles directed to data in the DRAM array. Control information, including a non-DRAM indicator in the case of data not stored in a DRAM array, are maintained for all read cycles. Returned data stored in a DRAM array and data not stored in a DRAM array are buffered together. When extracting read data from the buffer, data not stored in a DRAM array are identified by the non-DRAM indicator and directed to circuits within the controller. When data not stored in the DRAM array indicates the temperature of the SDRAM die, the controller may adjust the refresh rate in response to the temperature.Type: GrantFiled: June 23, 2005Date of Patent: December 29, 2009Assignee: QUALCOMM IncorporatedInventor: Robert Michael Walker
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Patent number: 7586805Abstract: A memory system is provided. The memory system includes a volatile memory having a number of banks and a memory controller configured to control the volatile memory to engage in an auto-refresh mode or a self-refresh mode. The memory controller is further configured to direct the volatile memory to perform an auto-refresh operation on a target bank. The remaining banks are available for access while the auto-refresh operation is being performed on the target bank.Type: GrantFiled: March 14, 2006Date of Patent: September 8, 2009Assignee: QUALCOMM IncorporatedInventors: Perry Willmann Remaklus, Jr., Robert Michael Walker
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Patent number: 7583552Abstract: A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile memory to engage in an auto-refresh mode, the memory controller further configured to provide a target bank address to the volatile memory. The volatile memory is configured to perform an auto-refresh operation in the auto-refresh mode, the auto-refresh operation being performed on a target bank identified by the target bank address. Remaining banks in the plurality of banks other than the target bank are available for memory access while the auto-refresh operation is being performed on the target bank.Type: GrantFiled: January 16, 2007Date of Patent: September 1, 2009Assignee: QUALCOMM IncorporatedInventors: Perry Willmann Remaklus, Jr., Robert Michael Walker
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Patent number: 7251192Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2?b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.Type: GrantFiled: January 16, 2007Date of Patent: July 31, 2007Assignee: QUALCOMM IncorporatedInventor: Robert Michael Walker
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Patent number: 7236416Abstract: A memory system for controlling memory refresh is provided. An embodiment of the memory system includes a memory configured to operate in a self-refresh mode and an auto-refresh mode, the memory having a plurality of memory locations, and a memory controller configured to access a first one of the memory locations while a second one of the memory locations is being refreshed in the auto-refresh mode. Another embodiment of the memory system includes a memory that can communicate its self refresh address to the memory controller. A further embodiment includes a memory controller that can communicate an auto-refresh address to a memory.Type: GrantFiled: February 10, 2005Date of Patent: June 26, 2007Assignee: Qualcomm IncorporatedInventor: Robert Michael Walker
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Patent number: 7230876Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2'b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.Type: GrantFiled: May 13, 2005Date of Patent: June 12, 2007Assignee: Qualcomm IncorporatedInventor: Robert Michael Walker
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Patent number: 7184350Abstract: A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile memory to engage in an auto-refresh mode, the memory controller further configured to provide a target bank address to the volatile memory. The volatile memory is configured to perform an auto-refresh operation in the auto-refresh mode, the auto-refresh operation being performed on a target bank identified by the target bank address. Remaining banks in the plurality of banks other than the target bank are available for memory access while the auto-refresh operation is being performed on the target bank.Type: GrantFiled: November 5, 2004Date of Patent: February 27, 2007Assignee: Qualcomm IncorporatedInventors: Perry Willmann Remaklus, Jr., Robert Michael Walker
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Method and system for providing seamless self-refresh for directed bank refresh in volatile memories
Patent number: 7088633Abstract: A memory system is provided. The system includes a volatile memory having a number of banks and configured to engage in one of a number of operating modes including an auto-refresh mode and a self-refresh mode, and a memory controller configured to direct the volatile memory to engage in one of the operating modes. Upon the memory controller directing the volatile memory to engage in the self-refresh mode, the memory controller is further configured to provide an entry bank address to the volatile memory, the entry bank address corresponding to the first bank that is to be refreshed during the self-refresh mode. Upon the volatile memory exiting the self-refresh mode, the volatile memory is further configured to make an exit bank address available to the memory controller, the exit bank address corresponding to the last bank that was refreshed prior to the volatile memory exiting the self-refresh mode.Type: GrantFiled: November 5, 2004Date of Patent: August 8, 2006Assignee: QUALCOMM IncorporatedInventors: Perry Willmann Remaklus, Jr., Robert Michael Walker -
Patent number: 7079440Abstract: A memory system is provided. The memory system includes a volatile memory having a number of banks and a memory controller configured to control the volatile memory to engage in an auto-refresh mode or a self-refresh mode. The memory controller is further configured to direct the volatile memory to perform an auto-refresh operation on a target bank. The remaining banks are available for access while the auto-refresh operation is being performed on the target bank.Type: GrantFiled: November 5, 2004Date of Patent: July 18, 2006Assignee: QUALCOMM IncorporatedInventors: Perry Willmann Remaklus, Jr., Robert Michael Walker