Patents by Inventor Robert MIGLIORINO

Robert MIGLIORINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11950361
    Abstract: A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include signal layers, ground plane layers, inner signal layers, and a single core substrate layer. Each of the layers may be separated from the other layers by at least one prepreg substrate layer.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 2, 2024
    Assignee: VEEA INC.
    Inventors: Shaun Joseph Greaney, Robert Migliorino, Michael Liccone, Clint Smith
  • Patent number: 11695238
    Abstract: Various embodiments include a connector head assembly for an electrical cable attached to one or more receptacle connectors. The connector head assembly may include an elongate overmold having a longitudinal extent that is longer than a height or width thereof. The elongate overmold may be configured to encase a terminal end of the electrical cable coupled to the one or more receptacle connectors inside the elongate overmold. The connector head assembly may also include a pull tab pivotally attached to the elongate overmold on an upper surface thereof. A pulling force applied to the pull tab may be configured to separate the receptacle connector from a receptacle in which the receptacle connector is configured to be held.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: July 4, 2023
    Assignee: VEEA INC.
    Inventors: Robert Migliorino, Michael Mirabella, Shaun Joseph Greaney, Michael Liccone
  • Publication number: 20230087792
    Abstract: A multiple layer printed circuit board including a plurality of layers, vertical interconnect accesses (VIAs), and a vertical interconnect access (VIA) bridge. The layers may include signal layers, prepreg substrate layers disposed between the signal layers, ground plane layers, wherein each of the ground plane layers abuts one of the prepreg substrate layers, inner signal layers, wherein each of the inner signal layers abuts one of the prepreg substrate layers, and a core substrate layer disposed between the signal layers, wherein two of the inner signal layers abut opposed sides of the core substrate layer. The VIAs extend through at least some of the layers, wherein each of the VIAs is formed by aligned apertures through adjoining ones of the prepreg substrate layers, ground plane layers, and inner signal layers. The VIA bridge is coupled to the VIAs to convey heat to a heat sink.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 23, 2023
    Inventors: Robert MIGLIORINO, Michael MIRABELLA, Clint SMITH
  • Publication number: 20230017840
    Abstract: A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include signal layers, ground plane layers, inner signal layers, and a single core substrate layer. Each of the layers may be separated from the other layers by at least one prepreg substrate layer.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 19, 2023
    Inventors: Shaun Joseph GREANEY, Robert MIGLIORINO, Michael LICCONE, Clint SMITH
  • Patent number: 11523502
    Abstract: A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include a plurality of layers that include a plurality of signal layers, a plurality of ground plane layers, a plurality of inner signal layers, and a single core substrate layer. Each layer in the plurality of layers may be separated from every other layer in the plurality of layers by at least one prepreg substrate layer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: December 6, 2022
    Assignee: VEEA INC.
    Inventors: Shaun Joseph Greaney, Robert Migliorino, Michael Liccone, Clint Smith
  • Publication number: 20210384675
    Abstract: Various embodiments include a connector head assembly for an electrical cable attached to one or more receptacle connectors. The connector head assembly may include an elongate overmold having a longitudinal extent that is longer than a height or width thereof. The elongate overmold may be configured to encase a terminal end of the electrical cable coupled to the one or more receptacle connectors inside the elongate overmold. The connector head assembly may also include a pull tab pivotally attached to the elongate overmold on an upper surface thereof. A pulling force applied to the pull tab may be configured to separate the receptacle connector from a receptacle in which the receptacle connector is configured to be held.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 9, 2021
    Inventors: Robert Migliorino, Michael Mirabella, Shaun Joseph Greaney, Michael Liccone
  • Publication number: 20210352802
    Abstract: A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include a plurality of layers that include a plurality of signal layers, a plurality of ground plane layers, a plurality of inner signal layers, and a single core substrate layer. Each layer in the plurality of layers may be separated from every other layer in the plurality of layers by at least one prepreg substrate layer.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 11, 2021
    Inventors: Shaun Joseph GREANEY, Robert MIGLIORINO, Michael LICCONE, Clint SMITH
  • Patent number: D1025047
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: April 30, 2024
    Assignee: VEEA INC.
    Inventors: Michael J. Mirabella, Robert Migliorino, Shaun Joseph Greaney