Patents by Inventor Robert Mounger

Robert Mounger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050035806
    Abstract: The present invention comprises a clamp circuit (104) comprised of a first transistor (111), a second transistor (112), a voltage divider circuit and a delay circuit (105) comprised of a fourth transistor (114), a fifth transistor (115), a sixth transistor (116) and a seventh transistor (117) and a fifth resistor (125), operable to keep the signals at the EEPROM input nodes (131) and (132) of a data cell, such as an EEPROM cell below a certain voltage threshold, preferable below 10 volts.
    Type: Application
    Filed: July 24, 2003
    Publication date: February 17, 2005
    Inventors: Alaa El-Sherif, Robert Mounger
  • Patent number: 6198329
    Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: March 6, 2001
    Assignee: Dallas Semiconductor Corporation
    Inventors: William Richard Ezell, Robert Mounger
  • Patent number: 6011417
    Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: January 4, 2000
    Assignee: Dallas Semiconductor Corporation
    Inventors: William Richard Ezell, Robert Mounger
  • Patent number: 5912548
    Abstract: An electronic device for monitoring the operating conditions of a rechargeable battery, and includes a temperature monitor for monitoring the operating temperature of the rechargeable battery; a voltage determiner coupled to the rechargeable battery for measuring the potential level of the rechargeable battery; a one wire interface for outputting the information corresponding to the potential level of the rechargeable battery and the information corresponding to the temperature monitored by the temperature monitor; and a power regulator coupled to the rechargeable battery for supplying regulated power from the rechargeable battery to the temperature monitor and the voltage determiner. The voltage determiner includes an analog to digital converter and utilizes a successive approximation technique to determine and output a digital value corresponding to the potential level of the rechargeable battery.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: June 15, 1999
    Assignee: Dallas Semiconductor Corp.
    Inventors: Richard E. Downs, Robert Mounger
  • Patent number: 5812005
    Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: September 22, 1998
    Assignee: Dallas Semiconductor Corp.
    Inventors: William Richard Ezell, Robert Mounger
  • Patent number: 5754037
    Abstract: The present invention regulates a power signal provided by a power source and includes two operational modes: a first mode capable of consuming low amounts of static power; and a second mode capable of smoothing voltage spikes appearing at high frequencies. The present invention further includes a generator, amplifier, and a regulator for controlling the power signal; a device for determining whether the present invention should be in the first or second operational mode; and a device for shifting between the first and second operational modes.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: May 19, 1998
    Assignee: Dallas Semiconductor Corporation
    Inventors: William Richard Ezell, Robert Mounger