Patents by Inventor Robert Munoz

Robert Munoz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11711268
    Abstract: Methods and apparatus to execute a workload in an edge environment are disclosed. An example apparatus includes a node scheduler to accept a task from a workload scheduler, the task including a description of a workload and tokens, a workload executor to execute the workload, the node scheduler to access a result of execution of the workload and provide the result to the workload scheduler, and a controller to access the tokens and distribute at least one of the tokens to at least one provider, the provider to provide a resource to the apparatus to execute the workload.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 25, 2023
    Assignee: INTEL CORPORATION
    Inventors: Ned Smith, Francesc Guim Bernat, Sanjay Bakshi, Katalin Bartfai-Walcott, Kapil Sood, Kshitij Doshi, Robert Munoz
  • Publication number: 20230095914
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die module coupled to the package substrate. In an embodiment, the die module comprises a die and a chiplet coupled to the die. In an embodiment, the chiplet is coupled to the die with a hybrid bonding interconnect architecture.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Gerald PASDAST, Sathya Narasimman TIAGARAJ, Adel A. ELSHERBINI, Tanay KARNIK, Robert MUNOZ, Kevin SAFFORD
  • Patent number: 10812402
    Abstract: Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Robert Southworth, Ben-Zion Friedman, Robert Munoz, Sarig Livne, Chih-Jen Chang, Yue Yang, Partick Fleming
  • Publication number: 20200167196
    Abstract: Methods and apparatus to execute a workload in an edge environment are disclosed. An example apparatus includes a node scheduler to accept a task from a workload scheduler, the task including a description of a workload and tokens, a workload executor to execute the workload, the node scheduler to access a result of execution of the workload and provide the result to the workload scheduler, and a controller to access the tokens and distribute at least one of the tokens to at least one provider, the provider to provide a resource to the apparatus to execute the workload.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 28, 2020
    Inventors: Ned Smith, Francesc Guim Bernat, Sanjay Bakshi, Katalin Bartfai-Walcott, Kapil Sood, Kshitij Doshi, Robert Munoz
  • Publication number: 20190140964
    Abstract: Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Robert Southworth, Ben-Zion Friedman, Robert Munoz, Sarig Livne, Chih-Jen Chang, Yue Yang, Partick Fleming
  • Publication number: 20070263619
    Abstract: A network device comprises a plurality of lookup tables and a processor. Each of the plurality of lookup tables comprises a plurality of table inputs that are associated with a plurality of processor instructions. The processor is operative to perform a network operation on a packet of data comprising a plurality of protocol header fields at least in part by performing one or more lookup cycles. A lookup cycle comprises the addressing of one of the plurality of lookup tables with one of the plurality of table inputs and the performing of the processor instruction associated with that table input. At least one of the plurality of processor instructions in the plurality of lookup tables comprises an instruction directing that the content of one of the plurality of protocol header fields be read and that one of the plurality of lookup tables be addressed with that content as the table input.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Inventor: Robert Munoz
  • Publication number: 20070115984
    Abstract: A network processor for determining one or more network operations to be performed on a packet of data in a network comprises processing circuitry and protocol indicator circuitry. The packet of data contains information populating a plurality of protocol header fields. Moreover, the protocol indicator circuitry comprises a plurality of memory elements, each memory element associated with a protocol header field in the plurality of protocol header fields. The processing circuitry determines the one or more network operations to be performed on the packet of data at least in part by addressing one or more lookup tables with the contents of a subset of the plurality of protocol header fields in the packet. This subset is determined by reference to the memory elements in the protocol indicator circuitry. Each memory element is capable of being programmed to indicate whether the associated protocol header field is to be utilized by the processing circuitry in addressing the one or more lookup tables.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 24, 2007
    Inventors: Vinoj Kumar, Robert Munoz
  • Publication number: 20070100386
    Abstract: The disclosure describes an axial lead connector assembly for an implantable medical device (IMD). The lead connector assembly facilitates electrical connection between an implantable medical lead and circuitry contained within the housing of an IMD. A connector header defines an axial stack bore to receive an axial stack of in-line connector components. The connector components define a common lead bore to receive a proximal end of an implantable lead. The in-line stack of connector components may include seals, electrical connector elements, a strain relief, and a locking device, each of which defines a passage that forms part of the lead bore.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Applicant: Medtronic, Inc.
    Inventors: Carole Tronnes, Robert Munoz, Alexander Lakanu, John Swoyer, Greg Theis, Bryan Zart, David DeSmet