Abstract: A method and apparatus for a cache line cut through reduces the latency and memory bandwidth of a data processing system. By cutting through or forwarding a cache line to the next processing element, data that has been read from a local memory into a local cache and altered by a processing element need not be restored to the local memory before it is sent to its destination target processing element. By eliminating the write back to the local memory for direct write through to the destination, performance is increased because the bandwidth and latency are decreased. In a preferred embodiment, the processing elements may be contained within a network processor and the altered data may be a header in one network protocol which needs to be modified to another protocol before transfer of the data along the network. Transfer of the data may be to another network processor, another processing element, or to another memory.

Abstract: A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set.