Patents by Inventor Robert N. Cooksey

Robert N. Cooksey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7260704
    Abstract: A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and the hit cache line is scanned for candidate virtual addresses in order to reinforce the prefetch chain.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: August 21, 2007
    Assignee: Intel Corporation
    Inventors: Robert N. Cooksey, Stephan J. Jourdan
  • Patent number: 7093077
    Abstract: A method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address. The first issued next-line prefetch request corresponds to a cache line having a memory address contiguous with the predicted memory address. Any subsequent next-line prefetch request corresponds to a cache line having a memory address contiguous with a memory address associated with a preceding next-line prefetch request.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: August 15, 2006
    Assignee: Intel Corporation
    Inventors: Robert N. Cooksey, Stephan J. Jourdan
  • Patent number: 6954840
    Abstract: A content prefetcher including a virtual address predictor. The virtual address predictor identifies candidate virtual addresses in a cache line without reference to an external address source.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: October 11, 2005
    Assignee: Intel Corporation
    Inventors: Robert N. Cooksey, Stephan J. Jourdan
  • Patent number: 6675280
    Abstract: A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized word in the cache line are compared with the upper bits of the cache line's effective address. If the upper bits of the address-sized word match the upper bits of the effective address, the address-sized word is identified as a candidate virtual address.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventors: Robert N. Cooksey, Stephan J. Jourdan
  • Publication number: 20030105940
    Abstract: A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and the hit cache line is scanned for candidate virtual addresses in order to reinforce the prefetch chain.
    Type: Application
    Filed: June 5, 2002
    Publication date: June 5, 2003
    Inventors: Robert N. Cooksey, Stephan J. Jourdan
  • Publication number: 20030105938
    Abstract: A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized word in the cache line are compared with the upper bits of the cache line's effective address. If the upper bits of the address-sized word match the upper bits of the effective address, the address-sized word is identified as a candidate virtual address.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 5, 2003
    Inventors: Robert N. Cooksey, Stephan J. Jourdan
  • Publication number: 20030105937
    Abstract: A content prefetcher including a virtual address predictor. The virtual address predictor identifies candidate virtual addresses in a cache line without reference to an external address source.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 5, 2003
    Inventors: Robert N. Cooksey, Stephan J. Jourdan
  • Publication number: 20030105939
    Abstract: A method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address. The first issued next-line prefetch request corresponds to a cache line having a memory address contiguous with the predicted memory address. Any subsequent next-line prefetch request corresponds to a cache line having a memory address contiguous with a memory address associated with a preceding next-line prefetch request.
    Type: Application
    Filed: June 5, 2002
    Publication date: June 5, 2003
    Inventors: Robert N. Cooksey, Stephan J. Jourdan