Patents by Inventor ROBERT NASRY HASBUN
ROBERT NASRY HASBUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210280225Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).Type: ApplicationFiled: March 25, 2021Publication date: September 9, 2021Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
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Publication number: 20210255958Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.Type: ApplicationFiled: February 23, 2021Publication date: August 19, 2021Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Patent number: 11010092Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.Type: GrantFiled: May 9, 2018Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Patent number: 11003388Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.Type: GrantFiled: August 29, 2018Date of Patent: May 11, 2021Assignee: Microon Technology, Inc.Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Patent number: 10978116Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).Type: GrantFiled: August 2, 2019Date of Patent: April 13, 2021Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
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Publication number: 20210105161Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
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Patent number: 10956333Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.Type: GrantFiled: August 20, 2018Date of Patent: March 23, 2021Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Patent number: 10942854Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.Type: GrantFiled: May 9, 2018Date of Patent: March 9, 2021Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Publication number: 20210041935Abstract: Systems, devices, and methods related to non-volatile memory are described. A non-volatile memory array may be employed as a main memory array for a system on a chip (SoC) or processor. A controller may interface between the non-volatile memory array and the SoC or processor using a protocol agnostic to characteristics of non-volatile memory operation including different page sizes or access time requirements, etc. A virtual memory bank at the controller may be employed to facilitate operations between the SoC or processor and the non-volatile memory array. The controller may be coupled with a buffer to facilitate rapid data operation, and the controller may be configured to selectively access data at the non-volatile array to account for data stored in the virtual memory bank or the buffer. The controller, the virtual memory bank, and the buffer may be configured on one chip separate from the SoC or processor.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventor: Robert Nasry Hasbun
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Patent number: 10904052Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.Type: GrantFiled: May 22, 2019Date of Patent: January 26, 2021Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
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Patent number: 10845866Abstract: Systems, devices, and methods related to non-volatile memory are described. A non-volatile memory array may be employed as a main memory array for a system on a chip (SoC) or processor. A controller may interface between the non-volatile memory array and the SoC or processor using a protocol agnostic to characteristics of non-volatile memory operation including different page sizes or access time requirements, etc. A virtual memory bank at the controller may be employed to facilitate operations between the SoC or processor and the non-volatile memory array. The controller may be coupled with a buffer to facilitate rapid data operation, and the controller may be configured to selectively access data at the non-volatile array to account for data stored in the virtual memory bank or the buffer. The controller, the virtual memory bank, and the buffer may be configured on one chip separate from the SoC or processor.Type: GrantFiled: June 22, 2017Date of Patent: November 24, 2020Assignee: Micron Technology, Inc.Inventor: Robert Nasry Hasbun
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Patent number: 10839874Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.Type: GrantFiled: August 29, 2018Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Patent number: 10832748Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.Type: GrantFiled: October 28, 2019Date of Patent: November 10, 2020Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
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Publication number: 20200348883Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.Type: ApplicationFiled: July 17, 2020Publication date: November 5, 2020Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Publication number: 20200327057Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
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Publication number: 20200294562Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Patent number: 10754578Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.Type: GrantFiled: May 9, 2018Date of Patent: August 25, 2020Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Patent number: 10725913Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.Type: GrantFiled: May 11, 2018Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
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Patent number: 10714159Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.Type: GrantFiled: May 9, 2018Date of Patent: July 14, 2020Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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Patent number: 10649687Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.Type: GrantFiled: August 27, 2018Date of Patent: May 12, 2020Assignee: Micron Technology, Inc.Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla