Abstract: A second transistor couples to a first transistor at a switch terminal. A third transistor couples to an auxiliary inductor terminal, and the third transistor also couples to the switch terminal. A logic circuit has a switch terminal, a first, a second, and a third input and first and second outputs. The first output couples to a control input of the third transistor. The second output couples to the second transistor. A configurable delay circuit has modulation, switch terminal, and voltage inputs and first, second, and third outputs. The switch terminal input couples to the switch terminal. The first output of a configurable delay circuit couples to the first input of the logic circuit. The second output of the configurable delay circuit couples to the second input of the logic circuit. The third output of the configurable delay circuit couples to the control input of the first transistor.

Abstract: A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The various phases may have different inherent frequencies that are synchronized to a common frequency such as an average of the different frequencies.

Abstract: A controller associated with a network connection includes a high speed local interface and a high overhead system interface. The controller can be a power controller for a power over Ethernet application. A controller for each connection is interconnected through the high speed interface. One of the controllers is configured at an address in the high overhead system interface to permit control instructions to be directed to the interconnected controllers from the host system. The architecture avoids the high overhead and complexity associated with multiple devices on the high overhead system interface and distributes processing and thermal loads among the controllers. The controller connected to the high overhead system interface can address the other controllers simply and rapidly to obtain a distributed control system for controlling power over network connections. The architecture reduces pin count, distributes thermal loads, reduces area requirements, and provides a flexible control solution.

Abstract: Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A power controller and physical link controller for the port share a high speed communication link to transfer information and control instructions from one to the other. The physical link controller provides digital functionality and processing capabilities that can generate power control instructions sent to the power controller over the high speed link. The power controller provides analog functionality for controlling the power supplied to the network connection and transfers power related information to the physical link controller over the high speed communication link and receives control instructions through a digital interface. The separation of digital of analog functionality simplifies the power control circuitry, removes redundancy, and frees valuable circuit board space for other desired functionality.

Abstract: Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor connected across the drain and the gate of the NMOS FET, an input resistor connected to the gate of the NMOS FET, level shifting circuitry connected between a positive output supply voltage and the input resistor, and a bias current source connected to the gate of the NMOS FET. A negative input supply voltage is connected to the source of the NMOS FET, and the negative output supply voltage is provided across a load connected to the drain of the NMOS FET. As the positive supply voltage ramps up from 0 to +VS, the level shifter provides a voltage to the input resistor that ramps up from ?VS to 0 volts. Further, the drain voltage of the NMOS FET ramps down from 0 to ?VS, thereby providing a negative output supply voltage ?VS with a slew rate that linearly tracks the slew rate of the master positive output supply.

Abstract: Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array coupled between the comparator inputs and multiple input voltage sources, a plurality of first switching elements, and control logic/drive circuitry coupled between the comparator output and the first switching elements. The first switching elements connect a selected input voltage source to a load. The comparator compares the voltage levels of the respective voltage sources, and provides a voltage indicating which one of the voltage sources is operational to the control logic/drive circuitry, which applies control signals to the first switching elements to connect the operational voltage source to the load. The symmetric resistor array and a plurality of second switching elements assure that symmetric trip voltages with hysteresis are provided to the comparator.

Abstract: Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor connected across the drain and the gate of the NMOS FET, an input resistor connected to the gate of the NMOS FET, level shifting circuitry connected between a positive output supply voltage and the input resistor, and a bias current source connected to the gate of the NMOS FET. A negative input supply voltage is connected to the source of the NMOS FET, and the negative output supply voltage is provided across a load connected to the drain of the NMOS FET. As the positive supply voltage ramps up from 0 to +VS, the level shifter provides a voltage to the input resistor that ramps up from ?VS to 0 volts. Further, the drain voltage of the NMOS FET ramps down from 0 to ?VS, thereby providing a negative output supply voltage ?VS with a slew rate that linearly tracks the slew rate of the master positive output supply.

Abstract: Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array coupled between the comparator inputs and multiple input voltage sources, a plurality of first switching elements, and control logic/drive circuitry coupled between the comparator output and the first switching elements. The first switching elements connect a selected input voltage source to a load. The comparator compares the voltage levels of the respective voltage sources, and provides a voltage indicating which one of the voltage sources is operational to the control logic/drive circuitry, which applies control signals to the first switching elements to connect the operational voltage source to the load. The symmetric resistor array and a plurality of second switching elements assure that symmetric trip voltages with hysteresis are provided to the comparator.