Abstract: An apparatus to facilitate weight lifting exercises is disclosed. The apparatus includes a palm plate having a hook portion configured to receive a weight bar. A detent is rotationally connected to the palm plate and configured to constrain the weight bar within the hook member in a closed position. An optional thumb lever may be connected to the detent to facilitate opening and closing the detent.

Abstract: An apparatus to facilitate weight lifting exercises is disclosed. The apparatus includes a palm plate having a hook portion configured to receive a weight bar. A detent is rotationally connected to the palm plate and configured to constrain the weight bar within the hook member in a closed position. An optional thumb lever may be connected to the detent to facilitate opening and closing the detent.

Abstract: A portable audio system with an integral hearing test is disclosed. The device includes a plurality of filter circuits. A processor applies a respective audio frequency to each filter circuit in a test mode to determine a respective gain based on a user input and applies the respective gain to each filter circuit in a normal mode. A switch circuit selects an audio signal from a plurality of sources in the normal mode. An analog-to-digital converter converts the selected audio signal to a digital signal and applies the digital signal to the plurality of filter circuits. A sum circuit receives a digital output signal from each of the plurality of filter circuits and produces a combined signal. A digital-to-analog converter converts the combined signal to an analog output signal.

Abstract: A portable audio system with an integral hearing test is disclosed. The device includes a plurality of filter circuits. A processor applies a respective audio frequency to each filter circuit in a test mode to determine a respective gain based on a user input and applies the respective gain to each filter circuit in a normal mode. A switch circuit selects an audio signal from a plurality of sources in the normal mode. An analog-to-digital converter converts the selected audio signal to a digital signal and applies the digital signal to the plurality of filter circuits. A sum circuit receives a digital output signal from each of the plurality of filter circuits and produces a combined signal. A digital-to-analog converter converts the combined signal to an analog output signal.

Abstract: An audio circuit with an integral hearing test is disclosed. The circuit includes at least one variable gain amplifier (VGA) coupled to receive an audio signal and a plurality of filters. Each filter is coupled to the at least one VGA and configured to filter an output signal from the at least one VGA. A processor is coupled to the VGAs and configured to apply a selected frequency to the at least one VGA in a test mode and to control a gain of the at least one VGA in a normal mode.

Abstract: An audio circuit with an integral hearing test is disclosed. The circuit includes at least one variable gain amplifier (VGA) coupled to receive an audio signal and a plurality of filters. Each filter is coupled to the at least one VGA and configured to filter an output signal from the at least one VGA. A processor is coupled to the VGAs and configured to apply a selected frequency to the at least one VGA in a test mode and to control a gain of the at least one VGA in a normal mode.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first region having a first conductivity type (410) is formed at a face of a substrate. A gate having a second conductivity type (406) is formed in the substrate beside the first region. A channel having the first conductivity type is formed below the first region adjacent the gate. A second region having the first conductivity type (404) is formed at the face of the substrate beside the gate. A third region having the first conductivity type (430) is formed below the channel and has a greater impurity concentration than the channel.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first region having a first conductivity type (410) is formed at a face of a substrate. A gate having a second conductivity type (406) is formed in the substrate beside the first region. A channel having the first conductivity type is formed below the first region adjacent the gate. A second region having the first conductivity type (404) is formed at the face of the substrate beside the gate. A third region having the first conductivity type (430) is formed below the channel and has a greater impurity concentration than the channel.

Abstract: A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal (310) and a second terminal (308). A first lightly doped region (304) having a first conductivity type (N?) is formed on a second lightly doped region (314) having a second conductivity type (P?). A first heavily doped region having the second conductivity type (P+) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region (400) having the second conductivity type (P+) is formed at least partially within the first lightly doped region at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first terminal (200), a first power supply terminal (Vdd), and a second power supply terminal (Vss). The circuit further includes a junction field effect transistor (JFET) having a current path coupled between the first terminal and the second power supply terminal. The JFET has a control terminal (202) coupled to the first power supply terminal.

Abstract: A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier (222, 224). The fuse is coupled between the voltage supply terminal and the semiconductor controlled rectifier. A switching circuit (200, 202, 208, 210) is coupled to the semiconductor controlled rectifier.

Abstract: A method of operating a memory circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The method includes selecting a word line (708) connected to a row of memory cells in response to a plurality of row address signals and selecting a plurality of columns (706,710) of memory cells in response to a plurality of column address signals. A first part (714) of the plurality of columns is selected in response to a first voltage applied to the selected word line. A second part (716) of the plurality of columns is selected in response to a second voltage applied to the selected word line.

Abstract: A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region (850,852) is formed in the substrate. The trench isolation region has sides and a bottom formed below a face of the substrate. A first semiconductor region having a second conductivity type (868) is formed at the bottom of the trench isolation region. A second semiconductor region having the second conductivity type (870) is formed separately from the first semiconductor region adjacent a first side of trench isolation region and in conductive contact with the first semiconductor region.

Abstract: A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier (222, 224). The fuse is coupled between the voltage supply terminal and the semiconductor controlled rectifier. A switching circuit (200, 202, 208, 210) is coupled to the semiconductor controlled rectifier.

Abstract: A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vp) and a latch circuit comprising a p-channel transistor and an n-channel transistor (208-214). A semiconductor controlled rectifier (206) in the circuit includes at least one terminal of the p-channel transistor. A fuse (200) is coupled between the voltage supply terminal and the semiconductor controlled rectifier. The fuse is programmed in response to the semiconductor controlled rectifier.

Abstract: A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region (850,852) is formed in the substrate. The trench isolation region has sides and a bottom formed below a face of the substrate. A first semiconductor region having a second conductivity type (868) is formed at the bottom of the trench isolation region. A second semiconductor region having the second conductivity type (870) is formed separately from the first semiconductor region adjacent a first side of trench isolation region and in conductive contact with the first semiconductor region.

Abstract: A method of operating a memory circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The method includes selecting a word line (708) connected to a row of memory cells in response to a plurality of row address signals and selecting a plurality of columns (706,710) of memory cells in response to a plurality of column address signals. A first part (714) of the plurality of columns is selected in response to a first voltage applied to the selected word line. A second part (716) of the plurality of columns is selected in response to a second voltage applied to the selected word line.

Abstract: A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vp) and a latch circuit comprising a p-channel transistor and an n-channel transistor (208-214). A semiconductor controlled rectifier (206) in the circuit includes at least one terminal of the p-channel transistor. A fuse (200) is coupled between the voltage supply terminal and the semiconductor controlled rectifier. The fuse is programmed in response to the semiconductor controlled rectifier.

Abstract: A method of protecting a power supply voltage in an integrated circuit is disclosed. The method includes storing charge in a charge reservoir capacitor (142), receiving a power supply sample voltage (140), and receiving a load power supply voltage (VDDL, 102). The power supply sample voltage is compared to the load power supply voltage (150). Charge is added from the charge reservoir capacitor (142) to the load power supply (VDDL) through transistor 126 and capacitor 144 in response to the step of comparing.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first terminal (200), a first power supply terminal (Vdd), and a second power supply terminal (Vss). The circuit further includes a junction field effect transistor (JFET) having a current path coupled between the first terminal and the second power supply terminal. The JFET has a control terminal (202) coupled to the first power supply terminal.