Patents by Inventor Robert O. Sharp
Robert O. Sharp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929927Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.Type: GrantFiled: December 21, 2020Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Pratik M. Marolia, Rajesh M. Sankaran, Ashok Raj, Nrupal Jani, Parthasarathy Sarangam, Robert O. Sharp
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Publication number: 20220360533Abstract: Methods, apparatus and software for implementing enhanced data center congestion management for non-TCP traffic. Non-congested transmit latencies are determined for transmission of packets or Ethernet frames along paths between source and destination end-end-nodes when congestion along the paths is not present or minimal. Transmit latencies are similarly measured along the same source-destination paths during ongoing operations during which traffic congestion may vary. Based on whether a difference between the transmit latency for a packet or frame and the non-congested transmit latency for the path exceeds a threshold, the path is marked as congested or not congested. A rate at which the non-TCP packets are transmitted along the path is then managed as function of a rate at which the path is marked as congested.Type: ApplicationFiled: May 24, 2022Publication date: November 10, 2022Inventors: Ygdal Naouri, Robert O. Sharp, Kenneth G. Keels, Eric W. Multanen
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Patent number: 11403137Abstract: Tenant support is provided in a multi-tenant configuration in a data center by a Physical Function driver communicating a virtual User Priority to a virtual traffic class mapper to a Virtual Function driver. The Physical Function driver configures the Network Interface Controller to map virtual User Priorities to Physical User Priorities and to enforce the Virtual Function's limited access to Traffic Classes. Data Center Bridging features assigned to the physical network interface controller are hidden by virtualizing user priorities and traffic classes. A virtual Data Center Bridging configuration is enabled for a Virtual Function, to provide access to the user priorities and traffic classes that are not visible to the Virtual Function that the Virtual Function may need.Type: GrantFiled: October 7, 2019Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Manasi Deval, Neerav Parikh, Robert O. Sharp, Gregory J. Bowers, Ryan E. Hall, Chinh T. Cao
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Patent number: 11025544Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.Type: GrantFiled: June 7, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Pratik M. Marolia, Rajesh M. Sankaran, Ashok Raj, Nrupal Jani, Parthasarathy Sarangam, Robert O. Sharp
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Publication number: 20210112003Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Pratik M. MAROLIA, Rajesh M. SANKARAN, Ashok RAJ, Nrupal JANI, Parthasarathy SARANGAM, Robert O. SHARP
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Publication number: 20210006511Abstract: Methods and apparatus for software-controlled active-backup mode of link aggregation for RDMA and virtual functions. A Network Interface Controller (NIC) includes hardware implementing first and second physical functions (PFs) including transmit and receive resources to support data transfers via first and second ports. A bonding group is created with the first and second PFs. The first PF as an active PF and used for primary data transfers while implementing the second PF as a backup PF. On a link or port failure of the active PF, the bonding group is reconfigured to employ transmit and receive resources of the backup PF such that those resources are shared with the active PF. Data transfers are then performed using the shared resources of the active PF and the backup PF. Embodiments may support RDMA data transfers using PF bonding and the solution may be implemented in virtualized environments including virtual machines (VMs) in a manner transparent to the VMs.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Inventors: Piotr Uminski, Anjali Singhai Jain, Eliel Louzoun, Robert O. Sharp, Vivek Kashyap
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Publication number: 20200319812Abstract: Examples described herein relate to accessing an initiator as a Non-Volatile Memory Express (NMVe) device. In some examples, the initiator is configured with an address space, configured in kernel or user space, for access by a virtualized execution environment. In some examples, the initiator to copy one or more storage access commands from the virtualized execution environment into a queue for access by a remote direct memory access (RDMA) compatible network interface. In some examples, the network interface to provide Non-Volatile Memory Express over Fabrics (NVMe-oF) compatible commands based on the one or more storage access commands to a target storage device. In some examples, the initiator is created as a mediated device in kernel space or user space of a host system. In some examples, configuration of a physical storage pool address of the target storage device for access by the virtualized execution environment occurs by receipt of the physical storage pool address in a configuration command.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Shaopeng HE, Yadong LI, Ziye YANG, Changpeng LIU, Banghao YING, Robert O. SHARP
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Publication number: 20200220816Abstract: Methods, apparatus and software for implementing enhanced data center congestion management for non-TCP traffic. Non-congested transmit latencies are determined for transmission of packets or Ethernet frames along paths between source and destination end-end-nodes when congestion along the paths is not present or minimal. Transmit latencies are similarly measured along the same source-destination paths during ongoing operations during which traffic congestion may vary. Based on whether a difference between the transmit latency for a packet or frame and the non-congested transmit latency for the path exceeds a threshold, the path is marked as congested or not congested. A rate at which the non-TCP packets are transmitted along the path is then managed as function of a rate at which the path is marked as congested.Type: ApplicationFiled: March 13, 2020Publication date: July 9, 2020Applicant: Intel CorporationInventors: Ygdal Naouri, Robert O. Sharp, Kenneth G. Keels, Eric W. Multanen
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Patent number: 10708187Abstract: Methods, apparatus and software for implementing enhanced data center congestion management for non-TCP traffic. Non-congested transit latencies are determined for transmission of packets or Ethernet frames along paths between source and destination end-end-nodes when congestion along the paths is not present or minimal. Transit latencies are similarly measured along the same source-destination paths during ongoing operations during which traffic congestion may vary. Based on whether a difference between the transit latency for a packet or frame and the non-congested transit latency for the path exceeds a threshold, the path is marked as congested or not congested. A rate at which the non-TCP packets are transmitted along the path is then managed as function of a rate at which the path is marked as congested.Type: GrantFiled: May 22, 2014Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Ygdal Naouri, Robert O. Sharp, Kenneth G. Keels, Eric W. Multanen
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Publication number: 20200042350Abstract: Tenant support is provided in a multi-tenant configuration in a data center by a Physical Function driver communicating a virtual User Priority to a virtual traffic class mapper to a Virtual Function driver. The Physical Function driver configures the Network Interface Controller to map virtual User Priorities to Physical User Priorities and to enforce the Virtual Function's limited access to Traffic Classes. Data Center Bridging features assigned to the physical network interface controller are hidden by virtualizing user priorities and traffic classes. A virtual Data Center Bridging configuration is enabled for a Virtual Function, to provide access to the user priorities and traffic classes that are not visible to the Virtual Function that the Virtual Function may need.Type: ApplicationFiled: October 7, 2019Publication date: February 6, 2020Inventors: Manasi DEVAL, Neerav PARIKH, Robert O. SHARP, Gregory J. BOWERS, Ryan E. HALL, Chinh T. CAO
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Patent number: 10467182Abstract: In an embodiment of the present invention, a method includes partitioning a plurality of remote direct memory access context objects among a plurality of virtual functions, establishing a remote direct memory access connection between a first of the plurality of virtual functions, and migrating the remote direct memory access connection from the first of the plurality of virtual functions to a second of the plurality of virtual functions without disconnecting from the remote peer.Type: GrantFiled: May 19, 2016Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Robert O. Sharp, Kenneth G. Keels
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Publication number: 20190297015Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.Type: ApplicationFiled: June 7, 2019Publication date: September 26, 2019Inventors: Pratik M. MAROLIA, Rajesh M. SANKARAN, Ashok RAJ, Nrupal JANI, Parthasarathy SARANGAM, Robert O. SHARP
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Patent number: 10051038Abstract: Generally, this disclosure relates to a shared send queue in a networked system. A method, apparatus and system are configured to support a plurality of reliable communication channels using a shared send queue. The reliable communication channels are configured to carry messages from a host to a plurality of destinations and to ensure completed order of messages is related to a transmission order.Type: GrantFiled: December 23, 2011Date of Patent: August 14, 2018Assignee: Intel CorporationInventors: Vadim Makhervaks, Robert O. Sharp, Brian Hausauer, Kenneth G. Keels, Donald E. Wood
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Patent number: 9558146Abstract: Apparatus, method and system for supporting Remote Direct Memory Access (RDMA) Read V2 Request and Response messages using the Internet Wide Area RDMA Protocol (iWARP). iWARP logic in an RDMA Network Interface Controller (RNIC) is configured to generate a new RDMA Read V2 Request message and generate a new RDMA Read V2 Response message in response to a received RDMA Read V2 Request message, and send the messages to an RDMA remote peer using iWARP implemented over an Ethernet network. The iWARP logic is further configured to process RDMA Read V2 Response messages received from the RDMA remote peer, and to write data contained in the messages to appropriate locations using DMA transfers from buffers on the RNIC into system memory. In addition, the new semantics removes the need for extra operations to grant and revoke remote access rights.Type: GrantFiled: July 18, 2013Date of Patent: January 31, 2017Assignee: Intel CorporationInventors: Robert O. Sharp, Donald E. Wood, Kenneth G. Keels
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Publication number: 20160267053Abstract: In an embodiment of the present invention, a method includes partitioning a plurality of remote direct memory access context objects among a plurality of virtual functions, establishing a remote direct memory access connection between a first of the plurality of virtual functions, and migrating the remote direct memory access connection from the first of the plurality of virtual functions to a second of the plurality of virtual functions without disconnecting from the remote peer.Type: ApplicationFiled: May 19, 2016Publication date: September 15, 2016Inventors: Robert O. Sharp, Kenneth G. Keels
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Patent number: 9411775Abstract: Apparatus, methods and systems for supporting Send with Immediate Data messages using Remote Direct Memory Access (RDMA) and the Internet Wide Area RDMA Protocol (iWARP). iWARP logic in an RDMA Network Interface Controller (RNIC) is configured to generate different types of Send with Immediate Data messages, each including a header with a unique RDMA opcode identifying the type of Send with Immediate Data message, and send the message to an RDMA remote peer using iWARP implemented over an Ethernet network. The iWARP logic is further configured to process the Send with Immediate Data messages received from the RDMA remote peer. The Send with Immediate Data messages include a Send with Immediate Data message, a Send with Invalidate and Immediate Data message, a Send with Solicited Event (SE) and Immediate Data message, and a Send with Invalidate and SE and Immediate Data message.Type: GrantFiled: July 24, 2013Date of Patent: August 9, 2016Assignee: Intel CorporationInventors: Robert O. Sharp, Donald E. Wood, Kenneth G. Keels
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Patent number: 9405725Abstract: An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred.Type: GrantFiled: September 29, 2011Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Vadim Makhervaks, Robert O. Sharp, Kenneth G. Keels, Brian S. Hausauer, Steen K. Larsen
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Patent number: 9354933Abstract: In an embodiment of the present invention, a method includes partitioning a plurality of remote direct memory access context objects among a plurality of virtual functions, establishing a remote direct memory access connection between a first of the plurality of virtual functions, and migrating the remote direct memory access connection from the first of the plurality of virtual functions to a second of the plurality of virtual functions without disconnecting from the remote peer.Type: GrantFiled: October 31, 2011Date of Patent: May 31, 2016Assignee: Intel CorporationInventors: Robert O. Sharp, Kenneth G. Keels
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Facilitating, at least in part, by circuitry, accessing of at least one controller command interface
Patent number: 9244881Abstract: An embodiment may include circuitry to facilitate, at least in part, a first network interface controller (NIC) in a client to be capable of accessing, via a second NIC in a server that is remote from the client and in a manner that is independent of an operating system environment in the server, at least one command interface of another controller of the server. The command interface may include at least one controller command queue. Such accessing may include writing at least one queue element to the at least one command queue to command the another controller to perform at least one operation associated with the another controller. The another controller may perform the at least one operation in response, at least in part, to the at least one queue element. Many alternatives, variations, and modifications are possible.Type: GrantFiled: March 4, 2015Date of Patent: January 26, 2016Assignee: Intel CorporationInventors: Eliezer Tamir, Ben-Zion Friedman, Theodore L. Willke, Eliel Louzoun, Matthew R. Wilcox, Donald E. Wood, Steven B. McGowan, Robert O. Sharp -
Publication number: 20150341273Abstract: Methods, apparatus and software for implementing enhanced data center congestion management for non-TCP traffic. Non-congested transmit latencies are determined for transmission of packets or Ethernet frames along paths between source and destination end-end-nodes when congestion along the paths is not present or minimal. Transmit latencies are similarly measured along the same source-destination paths during ongoing operations during which traffic congestion may vary. Based on whether a difference between the transmit latency for a packet or frame and the non-congested transmit latency for the path exceeds a threshold, the path is marked as congested or not congested. A rate at which the non-TCP packets are transmitted along the path is then managed as function of a rate at which the path is marked as congested.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Inventors: Ygdal Naouri, Robert O. Sharp, Kenneth G. Keels, Eric W. Multanen