Patents by Inventor Robert Ohannessian, Jr.

Robert Ohannessian, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10255075
    Abstract: A method, system and computer program product embodied on a computer-readable medium are provided for managing the execution of out-of-order instructions. The method includes the steps of receiving a plurality of instructions and identifying a subset of instructions in the plurality of instructions to be executed out-of-order.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: April 9, 2019
    Assignee: NVIDIA Corporation
    Inventors: Olivier Giroux, Robert Ohannessian, Jr., Jack H. Choquette, William Parsons Newhall, Jr.
  • Patent number: 10114755
    Abstract: A system, method, and computer program product for warming a cache for a task launch is described. The method includes the steps of receiving a task data structure that defines a processing task, extracting information stored in a cache warming field of the task data structure, and, prior to executing the processing task, generating a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: October 30, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Scott Ricketts, Nicholas Wang, Shirish Gadre, Gentaro Hirota, Robert Ohannessian, Jr.
  • Patent number: 9612836
    Abstract: A system, method, and computer program product are provided for implementing a software-based scoreboarding mechanism. The method includes the steps of receiving a dependency barrier instruction that includes an immediate value and an identifier corresponding to a first register and, based on a comparison of the immediate value to the value stored in the first register, dispatching a subsequent instruction to at least a first processing unit of two or more processing units.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 4, 2017
    Assignee: NVIDIA Corporation
    Inventors: Robert Ohannessian, Jr., Michael Alan Fetterman, Olivier Giroux, Jack H. Choquette, Xiaogang Qiu, Shirish Gadre, Meenaradchagan Vishnu
  • Patent number: 9477480
    Abstract: A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: October 25, 2016
    Assignee: NVIDIA Corporation
    Inventors: Olivier Giroux, Robert Ohannessian, Jr., Jack H. Choquette, Michael Alan Fetterman
  • Patent number: 9471307
    Abstract: A system and apparatus are provided that include an implementation for decoupled pipelines. The apparatus includes a scheduler configured to issue instructions to one or more functional units and a functional unit coupled to a queue having a number of slots for storing instructions. The instructions issued to the functional unit are stored in the queue until the functional unit is available to process the instructions.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: October 18, 2016
    Assignee: NVIDIA Corporation
    Inventors: Olivier Giroux, Michael Alan Fetterman, Robert Ohannessian, Jr., Shirish Gadre, Jack H. Choquette, Xiaogang Qiu, Jeffrey Scott Tuckey, Robert James Stoll
  • Publication number: 20150220341
    Abstract: A system, method, and computer program product are provided for implementing a software-based scoreboarding mechanism. The method includes the steps of receiving a dependency barrier instruction that includes an immediate value and an identifier corresponding to a first register and, based on a comparison of the immediate value to the value stored in the first register, dispatching a subsequent instruction to at least a first processing unit of two or more processing units.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: NVIDIA Corporation
    Inventors: Robert Ohannessian, JR., Michael Alan Fetterman, Olivier Giroux, Jack H. Choquette, Xiaogang Qiu, Shirish Gadre, Meenaradchagan Vishnu
  • Publication number: 20150212819
    Abstract: A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 30, 2015
    Applicant: NVIDIA Corporation
    Inventors: Olivier Giroux, Robert Ohannessian, JR., Jack H. Choquette, Michael Alan Fetterman
  • Publication number: 20150193272
    Abstract: A system and apparatus are provided that include an implementation for decoupled pipelines. The apparatus includes a scheduler configured to issue instructions to one or more functional units and a functional unit coupled to a queue having a number of slots for storing instructions. The instructions issued to the functional unit are stored in the queue until the functional unit is available to process the instructions.
    Type: Application
    Filed: January 3, 2014
    Publication date: July 9, 2015
    Applicant: NVIDIA Corporation
    Inventors: Olivier Giroux, Michael Alan Fetterman, Robert Ohannessian, JR., Shirish Gadre, Jack H. Choquette, Xiaogang Qiu, Jeffrey Scott Tuckey, Robert James Stoll
  • Publication number: 20150193358
    Abstract: A system includes a processing unit and a memory system coupled to the processing unit. The processing unit is configured to mark a memory access in the series of instructions as a priority memory access as a consequence of the memory access having a dependent instruction following less than a threshold distance after the memory access in the series of instructions. The processing unit is configured to send the marked memory access to the memory system.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: NVIDIA Corporation
    Inventors: James M. Van Dyke, Robert Ohannessian, JR.
  • Publication number: 20150026442
    Abstract: A method, system and computer program product embodied on a computer-readable medium are provided for managing the execution of out-of-order instructions. The method includes the steps of receiving a plurality of instructions and identifying a subset of instructions in the plurality of instructions to be executed out-of-order.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Applicant: NVIDIA Corporation
    Inventors: Olivier Giroux, Robert Ohannessian, Jr., Jack H. Choquette, William Parsons Newhall, Jr.
  • Publication number: 20140372703
    Abstract: A system, method, and computer program product for warming a cache for a task launch is described. The method includes the steps of receiving a task data structure that defines a processing task, extracting information stored in a cache warming field of the task data structure, and, prior to executing the processing task, generating a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Scott Ricketts, Nicholas Wang, Shirish Gadre, Gentaro Hirota, Robert Ohannessian, JR.
  • Patent number: 7663621
    Abstract: Circuits, methods, and apparatus that perform cylindrical wrapping in software without the need for a dedicated hardware circuit. One example performs cylindrical wrapping in software running on shader hardware. In one specific example, the shader hardware is a unified shader that alternately processes geometry, vertex, and fragment information. This unified shader is formed using a number of single-instruction, multiple-data units. Another example provides a method of performing a cylindrical wrap that ensures that a correct texture portion is used for a triangle that is divided by a “seam” of the wrap. To achieve this, primitive vertices are sorted such that results are vertex order invariant. One vertex is selected as a reference. For the other vertices, a difference is found for each coordinate and a corresponding coordinate of the reference vertex. If the coordinates are near, no change is made. If the coordinates are distant, the coordinate is adjusted.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: February 16, 2010
    Assignee: NVIDIA Corporation
    Inventors: Roger L. Allen, Harold Robert Zable, Robert Ohannessian, Jr.